Displaying 3 results from an estimated 3 matches for "vload_d".
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2017 Feb 21
2
Error at Pre-regalloc Machine LICM: "getVRegDef assumes a single definition or no definition"' failed.
...n idea why I'm getting the error below when using llc with
arguments -O1 -disable-cgp? Note that this error is not given when using llc -O0. (I'd
like to mention also I'm using custom Instruction selection for BUILD_VECTOR, which gets
converted in my back end's machine instrution VLOAD_D, although the custom code seems to
always select instructions in a valid way.)
******** Pre-regalloc Machine LICM: Test ********
Entering BB#4
Hoist non-reg-pressure: %vreg50<def> = VLOAD_D 1; MSA128D:%vreg50 dbg:IfVectorize.c:37:16
Hoisting %vreg50<def> = VLOAD_D...
2016 Jun 28
2
Instruction selection problem with type i64 - mistaken as v8i64?
...bove piece of code:
===== Instruction selection ends:
Selected selection DAG: BB#3 'foo:vector.body.preheader'
SelectionDAG has 11 nodes:
t0: ch = EntryToken
t1: i64 = MOV_ri TargetConstant:i64<0>
t3: ch = CopyToReg t0, Register:i64 %vreg23, t1
t11: v8i64 = VLOAD_D TargetConstant:i64<0>
t6: ch = CopyToReg t0, Register:v8i64 %vreg24, t11
t8: ch = TokenFactor t3, t6
t9: ch = JMP BasicBlock:ch<vector.body 0xa61440>, t8
[...]
Spilling live registers at end of block.
Spilling %vreg31 in %R0 to stack slot #5
Spilling %vreg32 in %Wd0 to...
2016 Jun 29
0
Instruction selection problem with type i64 - mistaken as v8i64?
...ruction selection ends:
> Selected selection DAG: BB#3 'foo:vector.body.preheader'
> SelectionDAG has 11 nodes:
> t0: ch = EntryToken
> t1: i64 = MOV_ri TargetConstant:i64<0>
> t3: ch = CopyToReg t0, Register:i64 %vreg23, t1
> t11: v8i64 = VLOAD_D TargetConstant:i64<0>
> t6: ch = CopyToReg t0, Register:v8i64 %vreg24, t11
> t8: ch = TokenFactor t3, t6
> t9: ch = JMP BasicBlock:ch<vector.body 0xa61440>, t8
>
> [...]
>
> Spilling live registers at end of block.
> Spilling %vreg31 in %R0 to st...