Displaying 3 results from an estimated 3 matches for "vlmul".
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2019 Feb 05
4
[RFC] Vector Predication
On 2/5/19 1:27 AM, Philip Reames via llvm-dev wrote:
>
> On 1/31/19 4:57 PM, Bruce Hoult wrote:
>> On Thu, Jan 31, 2019 at 4:05 PM Philip Reames via llvm-dev
>> <llvm-dev at lists.llvm.org> wrote:
>>> Do such architectures frequently have arithmetic operations on the
>>> mask registers? (i.e. can I reasonable compute a conservative
>>> length
2019 Feb 05
3
[RFC] Vector Predication
...d by the VSETVL[I] instruction which has
> two arguments: 1) the requested AVL, and 2) the vtype (vector type).
>
> - The vtype is an integer with several small fields, of which two are
> currently defined (the other bits must be zero). The fields are the
> Standard Element Width and VLMul. SEW can be any power of 2 from 8
> bits up to some implementation-defined maximum (1024 bits absolute
> maximum). VLMul says that you don't actually need 32 distinct vector
> variables in your current loop/function and you're willing to trade
> number of registers for a larger...
2019 Mar 18
6
Scalable Vector Types in IR - Next Steps?
On Fri, Mar 15, 2019 at 1:55 PM Chandler Carruth via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
>
> On Fri, Mar 15, 2019 at 11:22 AM Finkel, Hal J. via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>>
>> On 3/15/19 10:58 AM, David Greene wrote:
>> > Renato Golin <rengolin at gmail.com> writes:
>> >
>> >> On Fri, 15 Mar 2019 at