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Do you know any backend that implement instructions as a flag modifier in instruction ? Thank, Vincent Lejeune ----- Mail original ----- > De : Jakob Stoklund Olesen <stoklund at 2pi.dk> > À : Vincent Lejeune <vljn at ovi.com> > Cc : "llvmdev at cs.uiuc.edu (LLVMdev at cs.uiuc.edu)" <llvmdev at cs.uiuc.edu> > Envoyé le : Lundi 6 août 2012 20h06 > Objet : Re: [LLVMdev] Register Coalescer does not preserve TargetFlag > > > On Aug 6, 2012, at 11:00 AM, Vincent Lejeune <v...

...this=0x7fffffffdd60, M=...) at PassManager.cpp:1684 #19 0x0000000000816ff3 in main (argc=4, argv=0x7fffffffe108) at llc.cpp:362 Thank for your fast answer Regards, Vincent >________________________________ > De : Jakob Stoklund Olesen <stoklund at 2pi.dk> >À : Vincent Lejeune <vljn at ovi.com> >Cc : "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> >Envoyé le : Dimanche 21 octobre 2012 0h05 >Objet : Re: [LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers > > > > >On Oct 20, 2012, at 1:23 PM, Vincent Lejeune <vl...

Hi, R600 hardware (Radeon gfx card) does neither have a NEG nor an ABS instruction ; however any sources operand can be negated/abs'd by setting a bit for every source operand in the final bytecode (but not DST). A good way of modeling this behavior in LLVM is by using TargetFlag on operand. Currently the R600 LLVM backend in Mesa lower NEG and ABS DAG instruction to a MOV + TargetFlag using

On Aug 6, 2012, at 11:00 AM, Vincent Lejeune <vljn at ovi.com> wrote: > Ok. > > I tried to do it using a pass after register allocation, lowering NEG/ABS instructions. > However I met a problem : apparently getNextOperandForReg() can returns a MachineOperand before the one I'm processing. > > The following code snippet :...

On Oct 20, 2012, at 3:37 PM, Vincent Lejeune <vljn at ovi.com> wrote: > #5 0x00000000010c8e83 in (anonymous namespace)::JoinVals::getAssignments (this=0x7fffffffd230) at RegisterCoalescer.cpp:1305 Does this fix it? diff --git a/lib/CodeGen/RegisterCoalescer.cpp b/lib/CodeGen/RegisterCoalescer.cpp index ba6b456..2ca67d6 100644 --- a/lib/Co...

On Oct 20, 2012, at 1:23 PM, Vincent Lejeune <vljn at ovi.com> wrote: > below is an output of "llc -march=r600 -mcpu=cayman -print-before-all -debug-only=regalloc file.shader" command from llvm3.2svn. > The register coalescing pass crashes when joining vreg12:sel_z with vreg13 registers, because it tries to access the interval l...

On Aug 6, 2012, at 10:45 AM, Vincent Lejeune <vljn at ovi.com> wrote: > Is it possible to "customise" INSERT_SUBREG and COPY instructions to add them an immediate operands ? > I know that COPY is lowered using copyPhysReg() function in MachineTargetInstrInfo, but I'm not sure there is something equivalent for INSERT_SUBREG....

On Aug 6, 2012, at 11:12 AM, Vincent Lejeune <vljn at ovi.com> wrote: > Do you know any backend that implement instructions as a flag modifier in instruction ? No, I am not aware that any of the targets in the tree do something like that. TargetFlags is used by ARM to modify global symbol operands and such. But I meant you should be lookin...

Hi, The R600 backend uses the register coalescer pass to generate code. This pass has a EnablePhysicalJoin boolean value which is set to false by default. The way the R600 backend is used in Mesa runtime makes it very usefull to be set to true : We use live inst to represent OpenGL Input, which are converted to vreg = COPY %PhysReg after instruction selection. For instance, the following sample

...lt;BB#1>, pred:%noreg > Successors according to CFG: BB#1 > > # End machine code for function main. > ___________________________________________ > > > ----- Mail original ----- >> De : Ivan Llopard <ivanllopard at gmail.com> >> À : Vincent Lejeune <vljn at ovi.com> >> Cc : "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> >> Envoyé le : Jeudi 25 octobre 2012 21h54 >> Objet : Re: [LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG. >> >> Hi Vincent, >> >> On 25/10/2012 18:14, Vi...

...ll>; R600_Reg32:%vreg49,%vreg11 JUMP <BB#1>, pred:%noreg     Successors according to CFG: BB#1 # End machine code for function main. ___________________________________________ ----- Mail original ----- > De : Ivan Llopard <ivanllopard at gmail.com> > À : Vincent Lejeune <vljn at ovi.com> > Cc : "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> > Envoyé le : Jeudi 25 octobre 2012 21h54 > Objet : Re: [LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG. > > Hi Vincent, > > On 25/10/2012 18:14, Vincent Lejeune wrote: >&...

Hi Vincent, On 25/10/2012 18:14, Vincent Lejeune wrote: > When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg. > > If I look at the : > %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 > > instructions ; it gets joined to : > 928B%vreg34<def> = COPY %vreg48:sel_y; > > when vreg6 and

Hi, below is an output of "llc -march=r600 -mcpu=cayman -print-before-all -debug-only=regalloc file.shader" command from llvm3.2svn. The register coalescing pass crashes when joining vreg12:sel_z with vreg13 registers, because it tries to access the interval liveness of vreg13... which is undefined. I don't know if it's a bug of the pass, or if my backend should do something

...reg32:sel_x<def,read-undef> = COPY %vreg48:sel_x; R600_Reg128:%vreg32,%vreg48 updates it to  928B%vreg34<def> = COPY %vreg32:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg32 which is wrong. vreg32:sel_y is undef. Regards, Vincent ----- Mail original ----- > De : Vincent Lejeune <vljn at ovi.com> > À : Ivan Llopard <ivanllopard at gmail.com> > Cc : "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> > Envoyé le : Jeudi 25 octobre 2012 17h54 > Objet : Re: [LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG. > > > >>...

> > PHIElim and TwoAddress passes leave SSA form. > May be a missed something in your code but %vreg48 seems to be there > after PHI elimination. PHIElim tags those kind of registers as being > PHIJoin regs, updating LiveVariables pass, so the regcoalescer is aware > of them (some SSA info is still alive but the reg coalescer will > invalidate that information after

Hi, I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : // BEFORE LOOP ... Some COPYs.... 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2