Displaying 14 results from an estimated 14 matches for "vliwmachinescheduler".
2012 Aug 17
0
[LLVMdev] Assert in LiveInterval update
...ervalAnalysis.cpp:1226
#7 in llvm::LiveIntervals::HMEditor::moveAllRangesFrom
(this=0x7fffffff8010, MI=0x462ab80, OldIdx=...) at
lib/CodeGen/LiveIntervalAnalysis.cpp:938
#8 in llvm::LiveIntervals::handleMove (this=0x448b6f0, MI=0x462ab80) at
lib/CodeGen/LiveIntervalAnalysis.cpp:1388
#9 in llvm::VLIWMachineScheduler::moveInstruction (this=0x46b0f50,
MI=0x462ab80, InsertPos=...) at
lib/Target/Hexagon/HexagonMachineScheduler.cpp:120
#10 in llvm::VLIWMachineScheduler::schedule (this=0x46b0f50) at
lib/Target/Hexagon/HexagonMachineScheduler.cpp:378
#11 in (anonymous namespace)::MachineScheduler::runOnMachineFunc...
2012 Jun 12
2
[LLVMdev] Assert in live update from MI scheduler.
...ks this load:
%vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg10,%vreg9
To be scheduled first (!). Right there after
7 clang 0x000000000226aece
llvm::LiveIntervals::handleMove(llvm::MachineInstr*) + 378
8 clang 0x0000000001c2574f
llvm::VLIWMachineScheduler::listScheduleTopDown() + 595
9 clang 0x0000000001c24cd5 llvm::VLIWMachineScheduler::schedule()
+ 505
It does not seem to happen on the trunk.
My question is - Does anyone recognizes the issue, and what patch(es) do I
need to address it. Since my release is based on 3.1, I have to cherr...
2012 Aug 15
3
[LLVMdev] MI bundle liveness attributes
On Aug 13, 2012, at 8:34 AM, Sergei Larin <slarin at codeaurora.org> wrote:
> Andy,
>
> Yes, this is what Arnold has suggested also, and from this point it looks
> like it should work, but it will require parsing the bundle every time we
> care to know whether this is a real use or a conditional def. This might
> become awkward... but I guess I should provide a better
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...riw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
> IntRegs:%vreg10,%vreg9
>
> To be scheduled first (!). Right there after
>
> 7 clang 0x000000000226aece
> llvm::LiveIntervals::handleMove(llvm::MachineInstr*) + 378
> 8 clang 0x0000000001c2574f
> llvm::VLIWMachineScheduler::listScheduleTopDown() + 595
> 9 clang 0x0000000001c24cd5 llvm::VLIWMachineScheduler::schedule()
> + 505
>
> It does not seem to happen on the trunk.
>
> My question is - Does anyone recognizes the issue, and what patch(es) do I
> need to address it. Since my relea...
2012 Jun 11
0
[LLVMdev] scoreboard hazard det. and instruction groupings
On Jun 11, 2012, at 12:07 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> Looking at VLIWPacketizerList::PacketizeMIs, it seems like the
> instructions are first scheduled (via some external scheme?), and then
> packetized 'in order'. Is that correct?
Anshu?
> In the PowerPC grouping scheme, resources are assigned on a group
> basis (by the instruction dispatching
2016 Apr 27
2
Assertion in MachineScheduler.cpp
...::ConvergingVLIWScheduler::SchedCandidate&) + 284
14 clang-3.5 0x0000000000e4f2e5
llvm::ConvergingVLIWScheduler::pickNodeBidrectional(bool&) + 285
15 clang-3.5 0x0000000000e4f5b0
llvm::ConvergingVLIWScheduler::pickNode(bool&) + 576
16 clang-3.5 0x0000000000e4db8e
llvm::VLIWMachineScheduler::schedule() + 1366
17 clang-3.5 0x0000000001d7830f
18 clang-3.5 0x0000000001d77988
19 clang-3.5 0x0000000001d4f9c7
llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 95
20 clang-3.5 0x00000000014dacee
llvm::FPPassManager::runOnFunction(llvm::Function&) + 290...
2012 Aug 28
2
[LLVMdev] Assert in LiveInterval update
...llvm::LiveIntervals::HMEditor::moveAllRangesFrom
> (this=0x7fffffff8010, MI=0x462ab80, OldIdx=...) at
> lib/CodeGen/LiveIntervalAnalysis.cpp:938
> #8 in llvm::LiveIntervals::handleMove (this=0x448b6f0, MI=0x462ab80)
> at
> lib/CodeGen/LiveIntervalAnalysis.cpp:1388
> #9 in llvm::VLIWMachineScheduler::moveInstruction (this=0x46b0f50,
> MI=0x462ab80, InsertPos=...) at
> lib/Target/Hexagon/HexagonMachineScheduler.cpp:120
> #10 in llvm::VLIWMachineScheduler::schedule (this=0x46b0f50) at
> lib/Target/Hexagon/HexagonMachineScheduler.cpp:378
> #11 in (anonymous namespace)::MachineSc...
2012 Jun 13
4
[LLVMdev] Assert in live update from MI scheduler.
...tack.0.in]
> > IntRegs:%vreg10,%vreg9
> >
> > To be scheduled first (!). Right there after
> >
> > 7 clang 0x000000000226aece
> > llvm::LiveIntervals::handleMove(llvm::MachineInstr*) + 378
> > 8 clang 0x0000000001c2574f
> > llvm::VLIWMachineScheduler::listScheduleTopDown() + 595
> > 9 clang 0x0000000001c24cd5
> llvm::VLIWMachineScheduler::schedule()
> > + 505
> >
> > It does not seem to happen on the trunk.
> >
> > My question is - Does anyone recognizes the issue, and what patch(es)
> > d...
2016 Apr 27
2
Assertion in MachineScheduler.cpp
...>> 14 clang-3.5 0x0000000000e4f2e5
>> llvm::ConvergingVLIWScheduler::pickNodeBidrectional(bool&) + 285
>> 15 clang-3.5 0x0000000000e4f5b0
>> llvm::ConvergingVLIWScheduler::pickNode(bool&) + 576
>> 16 clang-3.5 0x0000000000e4db8e
>> llvm::VLIWMachineScheduler::schedule() + 1366
>> 17 clang-3.5 0x0000000001d7830f
>> 18 clang-3.5 0x0000000001d77988
>> 19 clang-3.5 0x0000000001d4f9c7
>> llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 95
>> 20 clang-3.5 0x00000000014dacee
>> llvm::F...
2012 Jun 11
3
[LLVMdev] scoreboard hazard det. and instruction groupings
On Mon, 11 Jun 2012 10:48:18 -0700
Andrew Trick <atrick at apple.com> wrote:
> On Jun 11, 2012, at 9:30 AM, Hal Finkel <hfinkel at anl.gov> wrote:
>
> > I'm considering writing more-detailed itineraries for some PowerPC
> > CPUs that use the 'traditional' instruction grouping scheme. In
> > essence, this means that multiple instructions will stall
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...0,%vreg9
> > >
> > > To be scheduled first (!). Right there after
> > >
> > > 7 clang 0x000000000226aece
> > > llvm::LiveIntervals::handleMove(llvm::MachineInstr*) + 378
> > > 8 clang 0x0000000001c2574f
> > > llvm::VLIWMachineScheduler::listScheduleTopDown() + 595
> > > 9 clang 0x0000000001c24cd5
> > llvm::VLIWMachineScheduler::schedule()
> > > + 505
> > >
> > > It does not seem to happen on the trunk.
> > >
> > > My question is - Does anyone recognizes the is...
2016 Apr 28
4
Assertion in MachineScheduler.cpp
...e4f2e5
> llvm::ConvergingVLIWScheduler::pickNodeBidrectional(bool&) + 285
> 15 clang-3.5 0x0000000000e4f5b0
> llvm::ConvergingVLIWScheduler::pickNode(bool&) + 576
> 16 clang-3.5 0x0000000000e4db8e
> llvm::VLIWMachineScheduler::schedule() + 1366
> 17 clang-3.5 0x0000000001d7830f
> 18 clang-3.5 0x0000000001d77988
> 19 clang-3.5 0x0000000001d4f9c7
> llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 95
> 20 clang-3.5...
2016 Apr 27
2
Assertion in MachineScheduler.cpp
I was handed a makefile which is used to compile a library and was told to
figure out why the compilation is failing.
There is a lot of output and at this point I'm not sure what is important
and what is not. I'm trying to solve this problem in small steps, so if
asked I can certainly provide more information.
The first error that I see during compilation is
2013 Sep 26
1
[LLVMdev] Enabling MI Scheduler on x86 (was Experimental Evaluation of the Schedulers in LLVM 3.3)
Hi,
Thanks for your explanations!
How is the big picture for supporting in-order VLIW architectures and
the like though?
I am asking because I am currently implementing instruction scheduling
in our own backend for our custom Patmos processor, for which I need to
support both branch delay slots and bundles, some restrictions regarding
bundles.
For the moment, I am quite happy with a simple