search for: vlen_stat

...n instead. You'd perform SSA construction only at the backend/legalization phase. Vice versa coming from IR targeted at LLVM SVE, you can go the other way, run a demanded vlen analysis, and encode it explicitly in the program. vlen changes are expensive and should be rare anyway. ; explicit vlen_state modelling in RV could look like this: @vlen_state=thread_local globaltoken ; this gives AA a fixed point to constraint vlen-dependent operations llvm.vla.setvl(i32 %n)                  ; implicitly writes-only %vlen_state i32 llvm.vla.getvl()                    ; implicitly reads-only %vlen_sta...

Hi, Now that Sander has committed enough MC support for SVE, here's an updated RFC for variable length vector support with a set of 14 patches (listed at the end) to demonstrate code generation for SVE using the extensions proposed in the RFC. I have some ideas about how to support RISC-V's upcoming extension alongside SVE; I'll send an email with some additional comments on