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vldr
2013 Jun 19
0
[LLVMdev] Vector type LOAD/STORE with post-increment.
...nged and lowered,
all of which change daily.
The quickest and surest way to generate NEON instructions is with NEON
intrinsics, but even so, LLVM is allowed to twist your code to generate
better instructions than you have thought possible. You can try to create
an IR that can generate post-indexed VLDRs on ARM, but that will not
guarantee it'll generate the same on any other backend.
A code that will generate post-indexed loads in ARM, might generate a
completely different instruction on Intel, or on your backend. What you
have to do is to understand the patterns that vectorized code has in I...
2013 Jun 19
3
[LLVMdev] Vector type LOAD/STORE with post-increment.
I am trying to implement vector type load/store with post-increment for an
out of tree backend.
I see that that ARM NEON support such load/store so I am using ARM NEON as
an example of what to do.
The problem is I can't get any C or C++ code example to actually generate
vector load/store with post increment.
I am talking about something like this:
vldr d16, [sp, #8]
Does anybody