search for: vlapic_has_pending_irq

From: Yang Zhang <yang.z.zhang@Intel.com> The following patches fix the issue that fail to boot L2 guest on APIC-v available machine. The main problem is that with APIC-v, virtual interrupt inject L1 is totally through APIC-v. But if virtual interrupt is arrived when L2 is running, L1 will detect interrupt through vmexit with reason external interrupt. If this happens, we should update

..., we do nothing but return at once because vioapic.redirtbl[2].mask = 1; Next, in vmx_intr_assist() -> hvm_vcpu_has_pending_irq(), we can''t inject vPIT interrupt because vlapic_accept_pic_intr() return false (because vlapic.lvt[LINT0].mask=1, and vlapic_hw_disabled() returns false), so vlapic_has_pending_irq() returns -1. Eventually, the pending PIT interrupts prevent the injection of lapic timer interrupts! The patch fixes the issue by rectifying is_isa_irq_masked(). Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> _______________________________________________ Xen-devel mailing list Xen-d...

...,6 +1011,14 @@ void vlapic_adjust_i8259_target(struct d pt_adjust_global_vcpu_target(v); } +int vlapic_virtual_intr_delivery_enabled(void) +{ + if ( hvm_funcs.virtual_intr_delivery_enabled ) + return hvm_funcs.virtual_intr_delivery_enabled(); + else + return 0; +} + int vlapic_has_pending_irq(struct vcpu *v) { struct vlapic *vlapic = vcpu_vlapic(v); @@ -1012,6 +1031,9 @@ int vlapic_has_pending_irq(struct vcpu * if ( irr == -1 ) return -1; + if ( vlapic_virtual_intr_delivery_enabled() ) + return irr; + isr = vlapic_find_highest_isr(vlapic); isr =...