search for: vivt

...doing > DMA. Again, I wonder how this is every going to work with > hardware based virtio implementations. You mean dma_Xmb and friends? There's a new feature VIRTIO_F_IO_BARRIER that's being proposed for that. > Even worse I think this > is actually broken at least for VIVT event for virtualized > implementations. E.g. a KVM guest is going to access memory > using different virtual addresses than qemu, vhost might throw > in another different address space. I don't really know what VIVT is. Could you help me please? > c) bounce buffering >...

...doing > DMA. Again, I wonder how this is every going to work with > hardware based virtio implementations. You mean dma_Xmb and friends? There's a new feature VIRTIO_F_IO_BARRIER that's being proposed for that. > Even worse I think this > is actually broken at least for VIVT event for virtualized > implementations. E.g. a KVM guest is going to access memory > using different virtual addresses than qemu, vhost might throw > in another different address space. I don't really know what VIVT is. Could you help me please? > c) bounce buffering >...

On Thu, May 31, 2018 at 09:09:24AM +0530, Anshuman Khandual wrote: > On 05/24/2018 12:51 PM, Ram Pai wrote: > > On Wed, May 23, 2018 at 09:50:02PM +0300, Michael S. Tsirkin wrote: > >> subj: s/virito/virtio/ > >> > > ..snip.. > >>> machine_subsys_initcall_sync(pseries, tce_iommu_bus_notifier_init); > >>> + > >>> +bool

On Thu, May 31, 2018 at 09:09:24AM +0530, Anshuman Khandual wrote: > On 05/24/2018 12:51 PM, Ram Pai wrote: > > On Wed, May 23, 2018 at 09:50:02PM +0300, Michael S. Tsirkin wrote: > >> subj: s/virito/virtio/ > >> > > ..snip.. > >>> machine_subsys_initcall_sync(pseries, tce_iommu_bus_notifier_init); > >>> + > >>> +bool

...rring data to the device, and invalidate the cpu cache before transferring data from the device. Plus additional workarounds for speculation. Looks at the implementations and comments around the dma_sync_* calls. > > > Even worse I think this > > is actually broken at least for VIVT event for virtualized > > implementations. E.g. a KVM guest is going to access memory > > using different virtual addresses than qemu, vhost might throw > > in another different address space. > > I don't really know what VIVT is. Could you help me please? Virtuall...

...d virtio implementations. > > > > > > You mean dma_Xmb and friends? > > There's a new feature VIRTIO_F_IO_BARRIER that's being proposed > > for that. > > > > > > > Even worse I think this > > > is actually broken at least for VIVT event for virtualized > > > implementations. E.g. a KVM guest is going to access memory > > > using different virtual addresses than qemu, vhost might throw > > > in another different address space. > > > > I don't really know what VIVT is. Could you...

...the DMA API on older ARM platforms, where we've had people abusing the API or going beneath the API because "it does what they need it to", which then makes stuff much harder to change at architecture level. Last time it happened, it was when ARMv6 came along and ARM moved away from VIVT caches. The options were either to break the crap drivers and support ARMv6+ CPUs, or keep the crap drivers working and not support DMA in any shape or form on ARMv6+. Obviously, this was too important to for one or two abusive drivers to block, so I changed the architecture level /anyway/ and ju...

...; > > > > > You mean dma_Xmb and friends? > > > There's a new feature VIRTIO_F_IO_BARRIER that's being proposed > > > for that. > > > > > > > > > > Even worse I think this > > > > is actually broken at least for VIVT event for virtualized > > > > implementations. E.g. a KVM guest is going to access memory > > > > using different virtual addresses than qemu, vhost might throw > > > > in another different address space. > > > > > > I don't really know...

...rms. b) coherency On many architectures DMA is not cache coherent, and we need to invalidate and/or write back cache lines before doing DMA. Again, I wonder how this is every going to work with hardware based virtio implementations. Even worse I think this is actually broken at least for VIVT event for virtualized implementations. E.g. a KVM guest is going to access memory using different virtual addresses than qemu, vhost might throw in another different address space. c) bounce buffering Many DMA implementations can not address all physical memory due to addressing limitatio...

...tforms, where > we've had people abusing the API or going beneath the API because "it > does what they need it to", which then makes stuff much harder to change > at architecture level. > > Last time it happened, it was when ARMv6 came along and ARM moved away > from VIVT caches. The options were either to break the crap drivers > and support ARMv6+ CPUs, or keep the crap drivers working and not > support DMA in any shape or form on ARMv6+. > > Obviously, this was too important to for one or two abusive drivers to > block, so I changed the architectu...

...ne LAST_PKMAP PTRS_PER_PTE @@ -46,19 +46,32 @@ extern pte_t *pkmap_page_table; #ifdef ARCH_NEEDS_KMAP_HIGH_GET extern void *kmap_high_get(struct page *page); -#else + +static inline void *arch_kmap_local_high_get(struct page *page) +{ + if (IS_ENABLED(CONFIG_DEBUG_HIGHMEM) && !cache_is_vivt()) + return NULL; + return kmap_high_get(page); +} +#define arch_kmap_local_high_get arch_kmap_local_high_get + +#else /* ARCH_NEEDS_KMAP_HIGH_GET */ static inline void *kmap_high_get(struct page *page) { return NULL; } -#endif +#endif /* !ARCH_NEEDS_KMAP_HIGH_GET */ -/* - * The following f...

On 06/24/2014 07:33 PM, Alexandre Courbot wrote: > On 06/24/2014 07:02 PM, Russell King - ARM Linux wrote: >> On Tue, Jun 24, 2014 at 06:54:26PM +0900, Alexandre Courbot wrote: >>> From: Lucas Stach <dev at lynxeye.de> >>> >>> On architectures for which access to GPU memory is non-coherent, >>> caches need to be flushed and invalidated explicitly

On 2019/3/14 ??6:42, Michael S. Tsirkin wrote: >>>>> Which means after we fix vhost to add the flush_dcache_page after >>>>> kunmap, Parisc will get a double hit (but it also means Parisc >>>>> was the only one of those archs needed explicit cache flushes, >>>>> where vhost worked correctly so far.. so it kinds of proofs your

On 2019/3/14 ??6:42, Michael S. Tsirkin wrote: >>>>> Which means after we fix vhost to add the flush_dcache_page after >>>>> kunmap, Parisc will get a double hit (but it also means Parisc >>>>> was the only one of those archs needed explicit cache flushes, >>>>> where vhost worked correctly so far.. so it kinds of proofs your

Following up to the discussion in: https://lore.kernel.org/r/20200914204209.256266093 at linutronix.de and the second version of this: https://lore.kernel.org/r/20201029221806.189523375 at linutronix.de this series provides a preemptible variant of kmap_atomic & related interfaces. This is achieved by: - Removing the RT dependency from migrate_disable/enable() - Consolidating all

Following up to the discussion in: https://lore.kernel.org/r/20200914204209.256266093 at linutronix.de and the second version of this: https://lore.kernel.org/r/20201029221806.189523375 at linutronix.de this series provides a preemptible variant of kmap_atomic & related interfaces. This is achieved by: - Removing the RT dependency from migrate_disable/enable() - Consolidating all

Following up to the discussion in: https://lore.kernel.org/r/20200914204209.256266093 at linutronix.de and the second version of this: https://lore.kernel.org/r/20201029221806.189523375 at linutronix.de this series provides a preemptible variant of kmap_atomic & related interfaces. This is achieved by: - Removing the RT dependency from migrate_disable/enable() - Consolidating all