Displaying 6 results from an estimated 6 matches for "visittrunc".
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visitfptrunc
2012 May 23
2
[LLVMdev] Predicate registers/condition codes question
...eOp() may help you here. X86 does something similar.
I just tried these functions, and it seems like they are only
modifying the behavior of type promotions for a small subset of
operations (PromoteIntBinOp, PromoteIntShiftOp, PromoteExtend,
PromoteLoad, SimplifyBinOpWithSameOpcodeHands, visitSRL, visitTRUNCATE
that matter to the performance of i16 on X86.)
I don't like the "desirable" in the name of these functions: in the
case of Hexagon it is illegal to use an i8 predicate register for
anything else than setcc, brcond, and the logical ops: so doing the
conversion is a matter of correc...
2019 Feb 08
2
Unfolded additions of constants after promotion of @llvm.ctlz.i16 on SystemZ
...::CTLZ,
and it seems to figure out that the high bits of t17 are zero, as expected.
t17 is guaranteed to have a value between 48 and 64, so there could not
be any overflow here, even though I am not sure if that's the problem or
not... Should DAGCombiner::visitADD() handle this, or perhaps
visitTRUNCATE()?
Thanks for any help,
Jonas
2012 May 24
0
[LLVMdev] Predicate registers/condition codes question
...X86 does something similar.
>
> I just tried these functions, and it seems like they are only
> modifying the behavior of type promotions for a small subset of
> operations (PromoteIntBinOp, PromoteIntShiftOp, PromoteExtend,
> PromoteLoad, SimplifyBinOpWithSameOpcodeHands, visitSRL, visitTRUNCATE
> that matter to the performance of i16 on X86.)
>
> I don't like the "desirable" in the name of these functions: in the
> case of Hexagon it is illegal to use an i8 predicate register for
> anything else than setcc, brcond, and the logical ops: so doing the
> con...
2012 May 22
0
[LLVMdev] Predicate registers/condition codes question
Hi Sebastian,
On 22/05/2012 23:25, Sebastian Pop wrote:
> Hi Eli,
>
> On Thu, Mar 1, 2012 at 2:21 PM, Eli Friedman<eli.friedman at gmail.com> wrote:
>> On Tue, Feb 28, 2012 at 11:17 AM, Tony Linthicum<tlinth at codeaurora.org> wrote:
>>> Hey folks,
>>>
>>> We are having some difficulty with how we have been representing our
>>>
2012 May 22
2
[LLVMdev] Predicate registers/condition codes question
Hi Eli,
On Thu, Mar 1, 2012 at 2:21 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
> On Tue, Feb 28, 2012 at 11:17 AM, Tony Linthicum <tlinth at codeaurora.org> wrote:
>> Hey folks,
>>
>> We are having some difficulty with how we have been representing our
>> predicate registers, and wanted some advice from the list. First, we
>> had been
2012 May 24
3
[LLVMdev] Predicate registers/condition codes question
...gt;
> > I just tried these functions, and it seems like they are only
> > modifying the behavior of type promotions for a small subset of
> > operations (PromoteIntBinOp, PromoteIntShiftOp, PromoteExtend,
> > PromoteLoad, SimplifyBinOpWithSameOpcodeHands, visitSRL,
> > visitTRUNCATE that matter to the performance of i16 on X86.)
> >
> > I don't like the "desirable" in the name of these functions: in the
> > case of Hexagon it is illegal to use an i8 predicate register for
> > anything else than setcc, brcond, and the logical ops: so doi...