search for: visitmul

Hi, I am working on PR34474 and try to add a new optimization to InstCombine. Like in other parts of the visitMul function I add a Shl through the IR builder and create a new BinaryOp which I return from visitMul. If I understand correctly the new BinaryOp returned from visitMul should replace the original Instruction in the Worklist. However, I end up in an infinite loop and the Instruction I try to repl...

...01 AM, Haidl, Michael via llvm-dev > <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > > Hi, > > I am working on PR34474 and try to add a new optimization to > InstCombine. Like in other parts of the visitMul function I > add a Shl > through the IR builder and create a new BinaryOp which I > return from > visitMul. If I understand correctly the new BinaryOp > returned from > visitMul should replace the original Ins...

...> test case? > > ~Craig > > On Wed, Sep 13, 2017 at 10:01 AM, Haidl, Michael via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> Hi, >> >> I am working on PR34474 and try to add a new optimization to >> InstCombine. Like in other parts of the visitMul function I add a Shl >> through the IR builder and create a new BinaryOp which I return from >> visitMul. If I understand correctly the new BinaryOp returned from >> visitMul should replace the original Instruction in the Worklist. >> However, I end up in an infinite loop an...

...es that we still have. At least ARM/AARCH64 and X86 have cases that can hopefully be generalised and removed, but there will probably be a few legality/perf issues that will occur. Simon. > On 14 Sep 2017, at 06:23, Craig Topper <craig.topper at gmail.com> wrote: > > Probably in visitMUL in DAGCombiner.cpp to be target independent. Or in LowerMUL in X86ISelLowering.cpp to be X86 specific. > > Adding Simon. Simon, which were you thinking? > > ~Craig > > On Wed, Sep 13, 2017 at 10:06 PM, Haidl, Michael <michael.haidl at uni-muenster.de <mailto:michael.haidl...

...gt; generalised and removed, but there will probably be a few legality/perf > issues that will occur. > > Simon. > >> On 14 Sep 2017, at 06:23, Craig Topper <craig.topper at gmail.com >> <mailto:craig.topper at gmail.com>> wrote: >> >> Probably in visitMUL in DAGCombiner.cpp to be target independent. Or >> in LowerMUL in X86ISelLowering.cpp to be X86 specific. >> >> Adding Simon. Simon, which were you thinking? >> >> ~Craig >> >> On Wed, Sep 13, 2017 at 10:06 PM, Haidl, Michael >> <michael.haidl at...

...> issues that will occur. > > Simon. > >> On 14 Sep 2017, at 06:23, Craig Topper <craig.topper at gmail.com<mailto:craig.topper at gmail.com> >> <mailto:craig.topper at gmail.com<mailto:craig.topper at gmail.com>>> wrote: >> >> Probably in visitMUL in DAGCombiner.cpp to be target independent. Or >> in LowerMUL in X86ISelLowering.cpp to be X86 specific. >> >> Adding Simon. Simon, which were you thinking? >> >> ~Craig >> >> On Wed, Sep 13, 2017 at 10:06 PM, Haidl, Michael >> <michael.haidl at u...

...re will probably be a few legality/perf > > issues that will occur. > > > > Simon. > > > >> On 14 Sep 2017, at 06:23, Craig Topper <craig.topper at gmail.com > >> <mailto:craig.topper at gmail.com>> wrote: > >> > >> Probably in visitMUL in DAGCombiner.cpp to be target independent. Or > >> in LowerMUL in X86ISelLowering.cpp to be X86 specific. > >> > >> Adding Simon. Simon, which were you thinking? > >> > >> ~Craig > >> > >> On Wed, Sep 13, 2017 at 10:06 PM, Haidl, Mich...

Hi, I observed below behavior with Instruction combiner (visitMul Canonicalization) It tries to convert "(X+C1)*C2" to "X*C2+C1*C2" While transforming if operation is guaranteed to not overflow it does not reflect same property to transformed instructions. Consider following scenarios: 1) If input is ((X+C1)*C2)<nsw> Then post canonica...

Borja, In this situation, you need to find the place where shl is generated and add a check to see if shl is legal before allowing it to do the transform. Micah From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Borja Ferrer Sent: Sunday, August 26, 2012 11:49 AM To: llvmdev at cs.uiuc.edu Subject: [LLVMdev] Illegal node introduced by DAGCombiner after

Hello, I'm getting an instruction selection error because DAGCombiner is introducing an illegal node after the legalizeDAG phase. Basically this is what is going on: 1) During legalization, BR_JT gets expanded introducing a (mul x, 2). 2) After legalization (AfterLegalizeDAG), that (mul x, 2) is converted to an (shl x, 1). However, that shl node introduced is illegal, and since my custom

The LangRef says this for left shifts: "If the nsw keyword is present, then the shift produces a poison value if it shifts out any bits that disagree with the resultant sign bit." ... (1) followed by "As such, NUW/NSW have the same semantics as they would if the shift were expressed as a mul instruction with the same nsw/nuw bits in (mul %op1, (shl 1, %op2))." ... (2) But