Displaying 6 results from an estimated 6 matches for "visitand".
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2009 Jul 29
3
[LLVMdev] Vector logic regression in r73431
...vector code, and the asserts happen because a logic operation is attempted
between a vector and a scalar (which is not present in the original code,
but created by InstCombine).
It's caused by revision 73431. I was able to fix it by changing the
following (identical) lines in InstCombiner::visitAnd, visitOr and visitXor:
if (SimplifyDemandedInstructionBits(I))
return &I;
Into:
if (!isa<VectorType>(I.getType()) && SimplifyDemandedInstructionBits(I))
return &I;
Apparently SimplifyDemandedInstructionBits doesn't work correctly with
vector o...
2009 Jul 29
0
[LLVMdev] Vector logic regression in r73431
...ns<nicolas at capens.net> wrote:
> So could anyone who knows the ins and outs of this code have a look at how
> to make it handle vectors correctly? Or if that’s not an option right now,
> please revert the broken optimizations. Note that there might be more things
> affected than visitAnd, visitOr and vistXor, I’ve only been able to identify
> these so far with little knowledge of the actual code. I currently don’t
> have a reduced testcase, but if really necessary I can try to extract one.
Does the attached help?
-Eli
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Index: Instructi...
2008 Aug 20
1
[LLVMdev] new warning in InstructionCombining.cpp
/Volumes/mrs5/net/llvm/llvm/lib/Transforms/Scalar/
InstructionCombining.cpp: In member function
‘llvm::Instruction*<unnamed>::InstCombiner::visitAnd
(llvm::BinaryOperator&)’:
/Volumes/mrs5/net/llvm/llvm/lib/Transforms/Scalar/
InstructionCombining.cpp:3597: warning: ‘RHSCC’ may be used
uninitialized in this function
/Volumes/mrs5/net/llvm/llvm/lib/Transforms/Scalar/
InstructionCombining.cpp:3597: warning: ‘LHSCC’ may be used
uninitial...
2013 Jul 09
2
[LLVMdev] EVT::isRound on non-8-bit byte targets
I'm new to LLVM dev, but I have been working with a target with a
minimum addressable byte of 16-bits. I found that in
DAGCombiner::visitAND, EVT::isRound could create i8 loads on my 16-bit
target which are ultimately invalid. EVT::isRound appears to use a
hard-coded 8, rather than pulling the targets BitsPerByte field. Is this
a potential bug or is there a better way to address this? Hard coding a
16 in the isRound field fixes the i...
2013 Jul 09
0
[LLVMdev] EVT::isRound on non-8-bit byte targets
Hi Sam,
On 09/07/13 17:01, Sam Cristall wrote:
> I'm new to LLVM dev, but I have been working with a target with a
> minimum addressable byte of 16-bits. I found that in
> DAGCombiner::visitAND, EVT::isRound could create i8 loads on my 16-bit
> target which are ultimately invalid. EVT::isRound appears to use a
> hard-coded 8, rather than pulling the targets BitsPerByte field. Is this
> a potential bug or is there a better way to address this? Hard coding a
> 16 in the isRou...
2009 Jul 30
2
[LLVMdev] Vector logic regression in r73431
...icolas at capens.net> wrote:
> So could anyone who knows the ins and outs of this code have a look at
> how to make it handle vectors correctly? Or if that's not an option
> right now, please revert the broken optimizations. Note that there
> might be more things affected than visitAnd, visitOr and vistXor, I've
> only been able to identify these so far with little knowledge of the
> actual code. I currently don't have a reduced testcase, but if really
necessary I can try to extract one.
Does the attached help?
-Eli