search for: visitadde

Hi all, I've been working on a backend of our architecture and noticed llvm performs following combining although one of operands is FrameIndex. Combining: t114: i64 = add FrameIndex:i64<0>, Constant:i64<56> Creating new node: t121: i64 = or FrameIndex:i64<0>, Constant:i64<56> ... into: t121: i64 = or FrameIndex:i64<0>, Constant:i64<56> This

Hi everyone, I posted some questions related to implementing inference of nsw/nuw flags based on known icmp results to Bug 30428 ( https://llvm.org/bugs/show_bug.cgi?id=30428 ) and it was recommended that I engage a wider audience by coming here. The minimal context is the following, please see the bug report for more detail: > 1. If (X s< Y), then both X + 1 and Y - 1 are nsw. > 2.

Hi, SystemZ supports @llvm.ctlz.i64() natively with a single instruction (FLOGR), and lesser bitwidth versions of the intrinsic are promoted to i64. For some reason, this leads to unfolded additions of constants as shown below: This function: define i16 @fun(i16 %arg) {   %1 = tail call i16 @llvm.ctlz.i16(i16 %arg, i1 false)   ret i16 %1 } ,gives this optimized DAG as input to instruction

...was whittled down from a fixed point math test by bugpoint, and further simplified by hand.    The problem did not occur in 2.8. > (Removing the trivial branch makes the problem go away.) > > I'm not sure where to begin debugging it, so any pointers would be appreciated. DAGCombiner::visitADDE looks suspicious to me... specifically, the way ReplaceAllUsesOfValueWith is used. -Eli

Chris Lattner wrote: > > 1. The MachineInstrBuilder has methods to add register operand and > > immediate operand. However, what would be really nice is a method to add > > Value*. So, I would write: > > > > BuildMI(*BB, NM::add, 1).add(I.getOperand(0), I.getOperand(1)); > > > > and depending on whether the passed Value* is contant or instruction,

On Mon, 7 Jun 2004, Vladimir Prus wrote: > > If you do this (which I recommend for the first step), you'll notice that > > it produces pretty horrible code, as all immediates are copied into > > registers before they are used. In other words, instead of getting: > > > > R2 = add R1, 17 > > > > You'll get: > > > > R3 = mov 17 >

In both LLVM 2.9 and the current svn head, I get the following error when running llc % llc < fxp2.ll LLVM ERROR: Cannot select: 0xa5302b0: glue = carry_false [ID=7] on this code: target triple = "i386-pc-linux-gnu" define i32 @fxpadd(i32 %cl) { entry: %0 = zext i32 %cl to i128 %1 = zext i32 %cl to i128 %2 = add i128 %1, %0 br label %L1001510 L1001510:

On Fri, 4 Jun 2004, Vladimir Prus wrote: > Ok, I'm now trying to write instruction selector and have some questions > > 1. The MachineInstrBuilder has methods to add register operand and immediate > operand. However, what would be really nice is a method to add Value*. So, I > would write: > > BuildMI(*BB, NM::add, 1).add(I.getOperand(0), I.getOperand(1)); > >

Ok, I'm now trying to write instruction selector and have some questions 1. The MachineInstrBuilder has methods to add register operand and immediate operand. However, what would be really nice is a method to add Value*. So, I would write: BuildMI(*BB, NM::add, 1).add(I.getOperand(0), I.getOperand(1)); and depending on whether the passed Value* is contant or instruction, the add

Chris Lattner wrote: > The ultimate solution is to use a pattern matching instruction selector > (which we are working on). In the meantime, depending on how RISCy your > target is, it's pretty easy to get reasonable code with few special cases. > Usually this is enough: > > ... visitAdd(Instruction &I) { > > if (ConstantInt *C =

Hi, I tried creating intrinsics which are to be placeholders for a set of instructions which should not be executed by the backend. I get the following verifier error. The "indvar.next4" instruction being mentioned in the step wise debug is not present in the LLVM IR (i.e IR before application of my transformation Pass). As seen below the operands of this instructions causing