search for: virtio_console_fd

...+ } > + } > + } > + if (net_poll[NET_FD_VIRTIO_NET].revents & POLLERR) { > + mpsslog("%s: %s: POLLERR\n", __func__, mic->name); > + sleep(1); > + } > + } > +done: > + pthread_exit(NULL); > +} > + > +/* virtio_console */ > +#define VIRTIO_CONSOLE_FD 0 > +#define MONITOR_FD (VIRTIO_CONSOLE_FD + 1) > +#define MAX_CONSOLE_FD (MONITOR_FD + 1) /* must be the last one + 1 */ > +#define MAX_BUFFER_SIZE PAGE_SIZE > + > +static void * > +virtio_console(void *arg) > +{ > + static __u8 vcons_buf[2][PAGE_SIZE]; > + struct iovec...

...+ } > + } > + } > + if (net_poll[NET_FD_VIRTIO_NET].revents & POLLERR) { > + mpsslog("%s: %s: POLLERR\n", __func__, mic->name); > + sleep(1); > + } > + } > +done: > + pthread_exit(NULL); > +} > + > +/* virtio_console */ > +#define VIRTIO_CONSOLE_FD 0 > +#define MONITOR_FD (VIRTIO_CONSOLE_FD + 1) > +#define MAX_CONSOLE_FD (MONITOR_FD + 1) /* must be the last one + 1 */ > +#define MAX_BUFFER_SIZE PAGE_SIZE > + > +static void * > +virtio_console(void *arg) > +{ > + static __u8 vcons_buf[2][PAGE_SIZE]; > + struct iovec...

...t;name, __func__, __LINE__, + strerror(errno)); + break; + } + } + } + if (net_poll[NET_FD_VIRTIO_NET].revents & POLLERR) { + mpsslog("%s: %s: POLLERR\n", __func__, mic->name); + sleep(1); + } + } +done: + pthread_exit(NULL); +} + +/* virtio_console */ +#define VIRTIO_CONSOLE_FD 0 +#define MONITOR_FD (VIRTIO_CONSOLE_FD + 1) +#define MAX_CONSOLE_FD (MONITOR_FD + 1) /* must be the last one + 1 */ +#define MAX_BUFFER_SIZE PAGE_SIZE + +static void * +virtio_console(void *arg) +{ + static __u8 vcons_buf[2][PAGE_SIZE]; + struct iovec vcons_iov[2] = { + { .iov_base = vcons_buf[...

ChangeLog: ========= v1 => v2: a) License wording cleanup, sysfs ABI documentation, patch 1 refactoring into 3 smaller patches and function renames, as per feedback from Greg Kroah-Hartman. b) Use VRINGH infrastructure for accessing virtio rings from the host in patch 5, as per feedback from Michael S. Tsirkin. v1: Initial post @ https://lkml.org/lkml/2013/7/24/810 Description:

ChangeLog: ========= v1 => v2: a) License wording cleanup, sysfs ABI documentation, patch 1 refactoring into 3 smaller patches and function renames, as per feedback from Greg Kroah-Hartman. b) Use VRINGH infrastructure for accessing virtio rings from the host in patch 5, as per feedback from Michael S. Tsirkin. v1: Initial post @ https://lkml.org/lkml/2013/7/24/810 Description:

ChangeLog: ========= v2 => v3: a) Patch 1 data structure cleanups, header file include cleanups, IDA interface reuse and switching to device_create_with_groups(..) as per feedback from Greg Kroah-Hartman. b) Patch 7 signal documentation, sleep workaround removal and sysfs access API cleanups as per feedback from Michael S. Tsirkin. v1 => v2: @ http://lwn.net/Articles/563131/ a)

ChangeLog: ========= v2 => v3: a) Patch 1 data structure cleanups, header file include cleanups, IDA interface reuse and switching to device_create_with_groups(..) as per feedback from Greg Kroah-Hartman. b) Patch 7 signal documentation, sleep workaround removal and sysfs access API cleanups as per feedback from Michael S. Tsirkin. v1 => v2: @ http://lwn.net/Articles/563131/ a)

ChangeLog: ========= v2 => v3: a) Patch 1 data structure cleanups, header file include cleanups, IDA interface reuse and switching to device_create_with_groups(..) as per feedback from Greg Kroah-Hartman. b) Patch 7 signal documentation, sleep workaround removal and sysfs access API cleanups as per feedback from Michael S. Tsirkin. v1 => v2: @ http://lwn.net/Articles/563131/ a)

ChangeLog: ========= v2 => v3: a) Patch 1 data structure cleanups, header file include cleanups, IDA interface reuse and switching to device_create_with_groups(..) as per feedback from Greg Kroah-Hartman. b) Patch 7 signal documentation, sleep workaround removal and sysfs access API cleanups as per feedback from Michael S. Tsirkin. v1 => v2: @ http://lwn.net/Articles/563131/ a)

An Intel MIC X100 device is a PCIe form factor add-in coprocessor card based on the Intel Many Integrated Core (MIC) architecture that runs a Linux OS. It is a PCIe endpoint in a platform and therefore implements the three required standard address spaces i.e. configuration, memory and I/O. The host OS loads a device driver as is typical for PCIe devices. The card itself runs a bootstrap after

An Intel MIC X100 device is a PCIe form factor add-in coprocessor card based on the Intel Many Integrated Core (MIC) architecture that runs a Linux OS. It is a PCIe endpoint in a platform and therefore implements the three required standard address spaces i.e. configuration, memory and I/O. The host OS loads a device driver as is typical for PCIe devices. The card itself runs a bootstrap after