Displaying 10 results from an estimated 10 matches for "virtio_config_cooki".
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virtio_config_cookie
2013 Jul 25
1
[PATCH 4/5] Intel MIC Card Driver Changes for Virtio Devices.
...evice vdev;
+ struct mic_device_desc __iomem *desc;
+ struct mic_device_ctrl __iomem *dc;
+ struct mic_device *mdev;
+ void __iomem *vr[MIC_MAX_VRINGS];
+ int used_size[MIC_MAX_VRINGS];
+ struct completion reset_done;
+ struct mic_irq *virtio_cookie;
+ int c2h_vdev_db;
+};
+
+static struct mic_irq *virtio_config_cookie;
+#define to_micvdev(vd) container_of(vd, struct mic_vdev, vdev)
+
+static inline struct device *dev(struct mic_vdev *mvdev)
+{
+ return mvdev->vdev.dev.parent;
+}
+
+/* This gets the device's feature bits. */
+static u32 mic_get_features(struct virtio_device *vdev)
+{
+ unsigned int i, bit...
2013 Jul 25
1
[PATCH 4/5] Intel MIC Card Driver Changes for Virtio Devices.
...evice vdev;
+ struct mic_device_desc __iomem *desc;
+ struct mic_device_ctrl __iomem *dc;
+ struct mic_device *mdev;
+ void __iomem *vr[MIC_MAX_VRINGS];
+ int used_size[MIC_MAX_VRINGS];
+ struct completion reset_done;
+ struct mic_irq *virtio_cookie;
+ int c2h_vdev_db;
+};
+
+static struct mic_irq *virtio_config_cookie;
+#define to_micvdev(vd) container_of(vd, struct mic_vdev, vdev)
+
+static inline struct device *dev(struct mic_vdev *mvdev)
+{
+ return mvdev->vdev.dev.parent;
+}
+
+/* This gets the device's feature bits. */
+static u32 mic_get_features(struct virtio_device *vdev)
+{
+ unsigned int i, bit...
2013 Aug 21
10
[PATCH v3 0/7] Enable Drivers for Intel MIC X100 Coprocessors.
ChangeLog:
=========
v2 => v3:
a) Patch 1 data structure cleanups, header file include cleanups,
IDA interface reuse and switching to device_create_with_groups(..)
as per feedback from Greg Kroah-Hartman.
b) Patch 7 signal documentation, sleep workaround removal and sysfs
access API cleanups as per feedback from Michael S. Tsirkin.
v1 => v2: @ http://lwn.net/Articles/563131/
a)
2013 Aug 21
10
[PATCH v3 0/7] Enable Drivers for Intel MIC X100 Coprocessors.
ChangeLog:
=========
v2 => v3:
a) Patch 1 data structure cleanups, header file include cleanups,
IDA interface reuse and switching to device_create_with_groups(..)
as per feedback from Greg Kroah-Hartman.
b) Patch 7 signal documentation, sleep workaround removal and sysfs
access API cleanups as per feedback from Michael S. Tsirkin.
v1 => v2: @ http://lwn.net/Articles/563131/
a)
2013 Sep 05
16
[PATCH RESEND v3 0/7] Enable Drivers for Intel MIC X100 Coprocessors.
ChangeLog:
=========
v2 => v3:
a) Patch 1 data structure cleanups, header file include cleanups,
IDA interface reuse and switching to device_create_with_groups(..)
as per feedback from Greg Kroah-Hartman.
b) Patch 7 signal documentation, sleep workaround removal and sysfs
access API cleanups as per feedback from Michael S. Tsirkin.
v1 => v2: @ http://lwn.net/Articles/563131/
a)
2013 Sep 05
16
[PATCH RESEND v3 0/7] Enable Drivers for Intel MIC X100 Coprocessors.
ChangeLog:
=========
v2 => v3:
a) Patch 1 data structure cleanups, header file include cleanups,
IDA interface reuse and switching to device_create_with_groups(..)
as per feedback from Greg Kroah-Hartman.
b) Patch 7 signal documentation, sleep workaround removal and sysfs
access API cleanups as per feedback from Michael S. Tsirkin.
v1 => v2: @ http://lwn.net/Articles/563131/
a)
2013 Jul 25
16
[PATCH 0/5] Enable Drivers for Intel MIC X100 Coprocessors.
An Intel MIC X100 device is a PCIe form factor add-in coprocessor
card based on the Intel Many Integrated Core (MIC) architecture
that runs a Linux OS. It is a PCIe endpoint in a platform and therefore
implements the three required standard address spaces i.e. configuration,
memory and I/O. The host OS loads a device driver as is typical for
PCIe devices. The card itself runs a bootstrap after
2013 Jul 25
16
[PATCH 0/5] Enable Drivers for Intel MIC X100 Coprocessors.
An Intel MIC X100 device is a PCIe form factor add-in coprocessor
card based on the Intel Many Integrated Core (MIC) architecture
that runs a Linux OS. It is a PCIe endpoint in a platform and therefore
implements the three required standard address spaces i.e. configuration,
memory and I/O. The host OS loads a device driver as is typical for
PCIe devices. The card itself runs a bootstrap after
2013 Aug 08
10
[PATCH v2 0/7] Enable Drivers for Intel MIC X100 Coprocessors.
ChangeLog:
=========
v1 => v2:
a) License wording cleanup, sysfs ABI documentation, patch 1 refactoring
into 3 smaller patches and function renames, as per feedback from
Greg Kroah-Hartman.
b) Use VRINGH infrastructure for accessing virtio rings from the host
in patch 5, as per feedback from Michael S. Tsirkin.
v1: Initial post @ https://lkml.org/lkml/2013/7/24/810
Description:
2013 Aug 08
10
[PATCH v2 0/7] Enable Drivers for Intel MIC X100 Coprocessors.
ChangeLog:
=========
v1 => v2:
a) License wording cleanup, sysfs ABI documentation, patch 1 refactoring
into 3 smaller patches and function renames, as per feedback from
Greg Kroah-Hartman.
b) Use VRINGH infrastructure for accessing virtio rings from the host
in patch 5, as per feedback from Michael S. Tsirkin.
v1: Initial post @ https://lkml.org/lkml/2013/7/24/810
Description: