Displaying 7 results from an estimated 7 matches for "viommu_pci_reset".
2020 Sep 24
2
[PATCH v3 5/6] iommu/virtio: Support topology description in config space
...gt; +
> + if (pci_enable_device_mem(dev))
> + return;
> +
> + common_regs = pci_iomap(dev, cap.bar, 0);
> + if (!common_regs)
> + return;
> +
> + common_cfg = common_regs + cap.offset;
> +
> + /* Perform the init sequence before we can read the config */
> + ret = viommu_pci_reset(common_cfg);
I guess this is some special device-specific reset, not any kind of
standard PCI reset?
> + if (ret < 0) {
> + pci_warn(dev, "unable to reset device\n");
> + goto out_unmap_common;
> + }
> +
> + iowrite8(VIRTIO_CONFIG_S_ACKNOWLEDGE, &common_cfg-&g...
2020 Sep 24
2
[PATCH v3 5/6] iommu/virtio: Support topology description in config space
...gt; +
> + if (pci_enable_device_mem(dev))
> + return;
> +
> + common_regs = pci_iomap(dev, cap.bar, 0);
> + if (!common_regs)
> + return;
> +
> + common_cfg = common_regs + cap.offset;
> +
> + /* Perform the init sequence before we can read the config */
> + ret = viommu_pci_reset(common_cfg);
I guess this is some special device-specific reset, not any kind of
standard PCI reset?
> + if (ret < 0) {
> + pci_warn(dev, "unable to reset device\n");
> + goto out_unmap_common;
> + }
> +
> + iowrite8(VIRTIO_CONFIG_S_ACKNOWLEDGE, &common_cfg-&g...
2020 Aug 21
0
[PATCH v3 5/6] iommu/virtio: Support topology description in config space
..._PCI_CFG && bar > 0x5)
+ continue;
+
+ cap->bar = bar;
+ pci_read_config_dword(dev, pos + VPCI_FIELD(length),
+ &cap->length);
+ pci_read_config_dword(dev, pos + VPCI_FIELD(offset),
+ &cap->offset);
+
+ return pos;
+ }
+ return 0;
+}
+
+static int viommu_pci_reset(struct virtio_pci_common_cfg __iomem *cfg)
+{
+ u8 status;
+ ktime_t timeout = ktime_add_ms(ktime_get(), 100);
+
+ iowrite8(0, &cfg->device_status);
+ while ((status = ioread8(&cfg->device_status)) != 0 &&
+ ktime_before(ktime_get(), timeout))
+ msleep(1);
+
+ return s...
2020 Sep 04
1
[PATCH v3 5/6] iommu/virtio: Support topology description in config space
...p->bar = bar;
> + pci_read_config_dword(dev, pos + VPCI_FIELD(length),
> + &cap->length);
> + pci_read_config_dword(dev, pos + VPCI_FIELD(offset),
> + &cap->offset);
> +
> + return pos;
> + }
> + return 0;
> +}
> +
> +static int viommu_pci_reset(struct virtio_pci_common_cfg __iomem *cfg)
> +{
> + u8 status;
> + ktime_t timeout = ktime_add_ms(ktime_get(), 100);
> +
> + iowrite8(0, &cfg->device_status);
> + while ((status = ioread8(&cfg->device_status)) != 0 &&
> + ktime_before(ktime_get(), t...
2020 Aug 21
17
[PATCH v3 0/6] Add virtio-iommu built-in topology
Add a topology description to the virtio-iommu driver and enable x86
platforms.
Since [v2] we have made some progress on adding ACPI support for
virtio-iommu, which is the preferred boot method on x86. It will be a
new vendor-agnostic table describing para-virtual topologies in a
minimal format. However some platforms don't use either ACPI or DT for
booting (for example microvm), and will
2020 Aug 21
17
[PATCH v3 0/6] Add virtio-iommu built-in topology
Add a topology description to the virtio-iommu driver and enable x86
platforms.
Since [v2] we have made some progress on adding ACPI support for
virtio-iommu, which is the preferred boot method on x86. It will be a
new vendor-agnostic table describing para-virtual topologies in a
minimal format. However some platforms don't use either ACPI or DT for
booting (for example microvm), and will
2020 Sep 25
0
[PATCH v3 5/6] iommu/virtio: Support topology description in config space
...> + return;
> > +
> > + common_regs = pci_iomap(dev, cap.bar, 0);
> > + if (!common_regs)
> > + return;
> > +
> > + common_cfg = common_regs + cap.offset;
> > +
> > + /* Perform the init sequence before we can read the config */
> > + ret = viommu_pci_reset(common_cfg);
>
> I guess this is some special device-specific reset, not any kind of
> standard PCI reset?
Yes it's the virtio reset - writing 0 to the status register in the BAR.
Thanks,
Jean