Displaying 4 results from an estimated 4 matches for "viommu_cread".
Did you mean:
iommu_read
2019 Nov 22
1
[RFC 13/13] iommu/virtio: Add topology description to
...; + return -EOVERFLOW;
> + }
> +
> + pci_write_config_byte(dev, cfg + VPCI_FIELD(bar), cap->bar);
> + pci_write_config_dword(dev, cfg + VPCI_FIELD(length), length);
> + pci_write_config_dword(dev, cfg + VPCI_FIELD(offset), offset);
> + return 0;
> +}
> +
> +static u32 viommu_cread(struct pci_dev *dev, int cfg,
> + struct viommu_cap_config *cap, u32 length, u32 offset)
> +{
> + u8 val8;
> + u16 val16;
> + u32 val32;
> + int out = cfg + sizeof(struct virtio_pci_cap);
> +
> + if (viommu_switch_pci_cfg(dev, cfg, cap, length, offset))
> + return 0;
&...
2019 Nov 22
0
[RFC 13/13] iommu/virtio: Add topology description to
...n",
+ length, offset, cap->length);
+ return -EOVERFLOW;
+ }
+
+ pci_write_config_byte(dev, cfg + VPCI_FIELD(bar), cap->bar);
+ pci_write_config_dword(dev, cfg + VPCI_FIELD(length), length);
+ pci_write_config_dword(dev, cfg + VPCI_FIELD(offset), offset);
+ return 0;
+}
+
+static u32 viommu_cread(struct pci_dev *dev, int cfg,
+ struct viommu_cap_config *cap, u32 length, u32 offset)
+{
+ u8 val8;
+ u16 val16;
+ u32 val32;
+ int out = cfg + sizeof(struct virtio_pci_cap);
+
+ if (viommu_switch_pci_cfg(dev, cfg, cap, length, offset))
+ return 0;
+
+ switch (length) {
+ case 1:
+ pci_read_co...
2019 Nov 22
16
[RFC 00/13] virtio-iommu on non-devicetree platforms
I'm seeking feedback on multi-platform support for virtio-iommu. At the
moment only devicetree (DT) is supported and we don't have a pleasant
solution for other platforms. Once we figure out the topology
description, x86 support is trivial.
Since the IOMMU manages memory accesses from other devices, the guest
kernel needs to initialize the IOMMU before endpoints start issuing DMA.
2019 Nov 22
16
[RFC 00/13] virtio-iommu on non-devicetree platforms
I'm seeking feedback on multi-platform support for virtio-iommu. At the
moment only devicetree (DT) is supported and we don't have a pleasant
solution for other platforms. Once we figure out the topology
description, x86 support is trivial.
Since the IOMMU manages memory accesses from other devices, the guest
kernel needs to initialize the IOMMU before endpoints start issuing DMA.