search for: vioapic_irq_positive_edg

...IRQ0 rather than vlapic timer interrupt, because: 1) is_isa_irq_masked(v, 0) returns false due to vpic.imr.bit0 = 0; 2) the PIT''s pt->last_plt_gtime is less than vlapic timer''s -- at least I can see this on my hosts; However, in pt_update_irq() -> hvm_isa_irq_assert() -> vioapic_irq_positive_edge(), we do nothing but return at once because vioapic.redirtbl[2].mask = 1; Next, in vmx_intr_assist() -> hvm_vcpu_has_pending_irq(), we can''t inject vPIT interrupt because vlapic_accept_pic_intr() return false (because vlapic.lvt[LINT0].mask=1, and vlapic_hw_disabled() returns false),...