search for: vidmask

...a/drm/nouveau/include/nvkm/subdev/bios/volt.h b/drm/nouveau/include/nvkm/subdev/bios/volt.h index b0df610..0d91c24 100644 --- a/drm/nouveau/include/nvkm/subdev/bios/volt.h +++ b/drm/nouveau/include/nvkm/subdev/bios/volt.h @@ -13,8 +13,9 @@ struct nvbios_volt { u32 base; /* GPIO mode */ - u8 vidmask; - s16 step; + bool entry_based; + u8 vidmask; + s16 step; /* PWM mode */ u32 pwm_freq; diff --git a/drm/nouveau/nvkm/subdev/bios/volt.c b/drm/nouveau/nvkm/subdev/bios/volt.c index 81a47b2..77e7b75 100644 --- a/drm/nouveau/nvkm/subdev/bios/volt.c +++ b/drm/nouveau/nvkm/subdev/bios/volt.c @...

...au_volt_parse_bios(struct nouveau_bios *bios, + struct nouveau_volt *volt) +{ + struct nvbios_volt_entry ivid; + struct nvbios_volt info; + u8 ver, hdr, cnt, len; + u16 data; + int i; + + data = nvbios_volt_parse(bios, &ver, &hdr, &cnt, &len, &info); + if (data && info.vidmask && info.base && info.step) { + for (i = 0; i < info.vidmask + 1; i++) { + if (info.base >= info.min && + info.base <= info.max) { + volt->vid[volt->vid_nr].uv = info.base; + volt->vid[volt->vid_nr].vid = i; + volt->vid_nr++; + } + i...

On a very few GPUs with the voltage table version 0x50 we have to read out the VIDs out of the entries of the table, where all the other gpus are either PWM based or get a base and a step voltage out of the table header. Currently nouveau tried to autodetect this and actually doesn't parse the entries. This Series adds two things: 1. It parses the entries 2. It decides upon a field in the

...29c7a 100644 --- a/drm/nouveau/nvkm/subdev/volt/base.c +++ b/drm/nouveau/nvkm/subdev/volt/base.c @@ -195,14 +195,16 @@ nvkm_volt_parse_bios(struct nvkm_bios *bios, struct nvkm_volt *volt) data = nvbios_volt_parse(bios, &ver, &hdr, &cnt, &len, &info); if (data && info.vidmask && info.base && info.step && info.ranged) { nvkm_debug(subdev, "found ranged based VIDs\n"); - volt->min_uv = info.min; - volt->max_uv = info.max; + volt->min_uv = 0xffffffff; + volt->max_uv = 0; for (i = 0; i < info.vidmask + 1; i++) {...

...au_volt_parse_bios(struct nouveau_bios *bios, + struct nouveau_volt *volt) +{ + struct nvbios_volt_entry ivid; + struct nvbios_volt info; + u8 ver, hdr, cnt, len; + u16 data; + int i; + + data = nvbios_volt_parse(bios, &ver, &hdr, &cnt, &len, &info); + if (data && info.vidmask && info.base && info.step) { + for (i = 0; i < info.vidmask + 1; i++) { + if (info.base >= info.min && + info.base <= info.max) { + volt->vid[volt->vid_nr].uv = info.base; + volt->vid[volt->vid_nr].vid = i; + volt->vid_nr++; + } + i...

Some Tegra drivers might be compiled as kernel modules, and they need the fuse information for initialization. One example is the GK20A Nouveau driver. It needs the GPU speedo value to calculate frequency-voltage table. So export the tegra_sku_info. Signed-off-by: Vince Hsu <vinceh at nvidia.com> Acked-by: Alexandre Courbot <acourbot at nvidia.com> Acked-by: Thierry Reding <treding

Some Tegra drivers might be compiled as kernel modules, and they need the fuse information for initialization. One example is the GK20A Nouveau driver. It needs the GPU speedo value to calculate frequency-voltage table. So export the tegra_sku_info. Signed-off-by: Vince Hsu <vinceh at nvidia.com> Acked-by: Alexandre Courbot <acourbot at nvidia.com> Acked-by: Thierry Reding <treding

The first patch is also part of my reclocking series Karol Herbst (2): volt: save the voltage range we are able to set hwmon: add in_min and in_max drm/nouveau/include/nvkm/subdev/volt.h | 3 +++ drm/nouveau/nouveau_hwmon.c | 36 ++++++++++++++++++++++++++++++++++ drm/nouveau/nvkm/subdev/volt/base.c | 14 ++++++++++++- 3 files changed, 52 insertions(+), 1 deletion(-) --

...ex 7143ea46..33a9fb5a 100644 --- a/drm/nouveau/nvkm/subdev/bios/volt.c +++ b/drm/nouveau/nvkm/subdev/bios/volt.c @@ -96,6 +96,8 @@ nvbios_volt_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, info->min = min(info->base, info->base + info->step * info->vidmask); info->max = nvbios_rd32(bios, volt + 0x0e); + if (!info->max) + info->max = max(info->base, info->base + info->step * info->vidmask); break; case 0x50: info->min = nvbios_rd32(bios, volt + 0x0a); -- 2.21.0

This series fixes most of the issues regarding volting on GPUs with any form of GPU Boost inside their vbios, which is mainly Kepler and newer, but we find some boosting related tables in Fermi vbios' already In the end reclocking should work on most Kepler cards without any issues Karol Herbst (19): bios/volt: handle voltage table version 0x50 with 0ed header volt: properly detect entry

This series fixes most of the issues regarding volting on GPUs with any form of GPU Boost inside their vbios, which is mainly Kepler and newer, but we find some boosting related tables in Fermi vbios' already In the end reclocking should work on most Kepler cards without any issues v2: boost_mode can now be changed at runtime minor fixups Karol Herbst (22): bios/volt: handle voltage

Some Tegra drivers might be complied as kernel modules, and they need the fuse information for initialization. One example is the GK20A Nouveau driver. It needs the GPU speedo value to calculate frequency-voltage table. So export the tegra_sku_info. Signed-off-by: Vince Hsu <vinceh at nvidia.com> --- v2: add more description why we need this patch drivers/soc/tegra/fuse/fuse-tegra.c | 1

This is an updated series for the old clocking improvement one. I think I got everything needed in place and also a simple update mechanism for updating the cstates/voltage on temperature changes. If anything is unclear how I REed or got the information, please leave a note so that I can provide additional information in the commits. Besides that I think we are pretty close now and only some

With these both patches, most of the kepler cards should be able to reclock their core clock without issues. These patches should be tested carefully among nouveau devs, so that these don't break reclocking on other cards (especially Teslas). Particularly the second one might break reclocking here and there. Karol Herbst (2): bios/volt: handle voltage table version 0x50 with 0ed header

.../nouveau/nvkm/subdev/volt/base.c > +++ b/drm/nouveau/nvkm/subdev/volt/base.c > @@ -195,14 +195,16 @@ nvkm_volt_parse_bios(struct nvkm_bios *bios, struct nvkm_volt *volt) > data = nvbios_volt_parse(bios, &ver, &hdr, &cnt, &len, &info); > if (data && info.vidmask && info.base && info.step && info.ranged) { > nvkm_debug(subdev, "found ranged based VIDs\n"); > - volt->min_uv = info.min; > - volt->max_uv = info.max; > + volt->min_uv = 0xffffffff; > + volt->max_uv = 0; > for (i = 0; i &...

...km/subdev/bios/volt.c index a7797a9e..7143ea46 100644 --- a/drm/nouveau/nvkm/subdev/bios/volt.c +++ b/drm/nouveau/nvkm/subdev/bios/volt.c @@ -93,9 +93,9 @@ nvbios_volt_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, info->step = nvbios_rd16(bios, volt + 0x08); info->vidmask = nvbios_rd08(bios, volt + 0x0b); info->ranged = true; /* XXX: find the flag byte */ - /*XXX*/ - info->min = 0; - info->max = info->base; + info->min = min(info->base, + info->base + info->step * info->vidmask); + info->max = nvbios_rd32...

...0644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c @@ -96,6 +96,8 @@ nvbios_volt_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, info->min = min(info->base, info->base + info->step * info->vidmask); info->max = nvbios_rd32(bios, volt + 0x0e); + if (!info->max) + info->max = max(info->base, info->base + info->step * info->vidmask); break; case 0x50: info->min = nvbios_rd32(bios, volt + 0x0a); -- 2.20.1

...0644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c @@ -96,6 +96,8 @@ nvbios_volt_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, info->min = min(info->base, info->base + info->step * info->vidmask); info->max = nvbios_rd32(bios, volt + 0x0e); + if (!info->max) + info->max = max(info->base, info->base + info->step * info->vidmask); break; case 0x50: info->min = nvbios_rd32(bios, volt + 0x0a); -- 2.20.1

...0644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c @@ -96,6 +96,8 @@ nvbios_volt_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, info->min = min(info->base, info->base + info->step * info->vidmask); info->max = nvbios_rd32(bios, volt + 0x0e); + if (!info->max) + info->max = max(info->base, info->base + info->step * info->vidmask); break; case 0x50: info->min = nvbios_rd32(bios, volt + 0x0a); -- 2.20.1

...0644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c @@ -96,6 +96,8 @@ nvbios_volt_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, info->min = min(info->base, info->base + info->step * info->vidmask); info->max = nvbios_rd32(bios, volt + 0x0e); + if (!info->max) + info->max = max(info->base, info->base + info->step * info->vidmask); break; case 0x50: info->min = nvbios_rd32(bios, volt + 0x0a); -- 2.20.1