search for: vhaddpsrm

...t;; > ... > > and > > let Predicates = [HasAVX] in { > def : Pat<(int_x86_sse3_hadd_ps (v4f32 VR128:$src1), VR128:$src2), > (VHADDPSrr VR128:$src1, VR128:$src2)>; > def : Pat<(int_x86_sse3_hadd_ps (v4f32 VR128:$src1), (memop addr:$src2)), > (VHADDPSrm VR128:$src1, addr:$src2)>; > ... I came up with a vim macro that added them for me (see attached patch). Probably there is a way to compress this using tablegen magic, but I don't know how. OK to apply? Ciao, Duncan. -------------- next part -------------- An embedded and charset-unspe...

...(HADDPSrm VR128:$src1, addr:$src2)>; ... and let Predicates = [HasAVX] in { def : Pat<(int_x86_sse3_hadd_ps (v4f32 VR128:$src1), VR128:$src2), (VHADDPSrr VR128:$src1, VR128:$src2)>; def : Pat<(int_x86_sse3_hadd_ps (v4f32 VR128:$src1), (memop addr:$src2)), (VHADDPSrm VR128:$src1, addr:$src2)>; ... Thanks Duncan, -- Bruno Cardoso Lopes http://www.brunocardoso.cc

...2)>; ... > > and > > let Predicates = [HasAVX] in { > def : Pat<(int_x86_sse3_hadd_ps (v4f32 VR128:$src1), VR128:$src2), > (VHADDPSrr VR128:$src1, VR128:$src2)>; def : > Pat<(int_x86_sse3_hadd_ps (v4f32 VR128:$src1), (memop addr:$src2)), > (VHADDPSrm VR128:$src1, addr:$src2)>; ... I came up with a vim macro that added them for me (see attached patch). Probably there is a way to compress this using tablegen magic, but I don't know how. OK to apply? Ciao, Duncan.

This patch synthesizes haddps/haddpd/hsubps/hsubpd instructions from floating point additions and subtractions of appropriate vector shuffles. To do this I introduced new x86 FHADD and FHSUB opcodes. These need to be wired up somehow in the .td file to the appropriate instructions. Since I have no idea how tablegen works I just hacked it in horribly. It works, but breaks support for the hadd