search for: vgprs

...the current MachineFunction). Presently CostPerUse is a one-time static value (either zero or a positive value) generated through table-gen. The current implementation doesn't allow us to control the reg-cost on the fly. The AMDGPU ABI has recently been revised by introducing more caller-saved VGPRs (the exact details are explained towards the end of this e-mail), and found that having a dynamic register cost is important to achieve an optical allocation. Precisely, it is important to limit the number of VGPRs allocated for a kernel/device-function to a smallest value since it will have a dire...

...CostPerUse is a one-time static value (either zero or a positive > value) generated through table-gen. > > The current implementation doesn’t allow us to control the reg-cost on the > fly. > > > > The AMDGPU ABI has recently been revised by introducing more caller-saved > VGPRs (the exact details are explained towards the end of this e-mail), and > found that having a dynamic register cost is important to achieve an > optical allocation. > > Precisely, it is important to limit the number of VGPRs allocated for a > kernel/device-function to a smallest value...

...just one sALU and one vALU. Programs written for Southern Islands intermix sALU and vALU instructions and all instructions are executed in order no matter what ALU the are executed on, so there is no synchronization needed between the ALUs. Each ALU has its own register file: SGPRs for sALU, and VGPRs for vALU. The vALU can read from VGPRs and also SGPRs, but the sALU can only read from SGPRs. This restriction on the sALU seems to be causing the instruction selector to generate some illegal copies, which is the main problem I'm trying to solve. For example: NODE0 = ISD::ADD SGPR0, VGPR0...

Hi Escha, Great to have your comment! Do you have any specific reason for not doing like this? I am not sure whether I understand your point correctly. For "just model one thread", do you mean "only considering ONE of the 8/16 working lanes that running in lock-step way"?? For my case, may be something like I only need to define r0~r127 as register for i32 register (each r#

...;: > If I understand right, on this arch, ‘uniform’ refers to values that only > take one lane of register file instead of SIMD-width lanes, and they > *share* the same region of the register file as non-uniform values. This is > in contrast to e.g. AMDGPU where SGPRs (scalar GPRs) and VGPRs are separate > register files. > > If this understanding is correct, you may be able to define uniform and > non-uniform registers separately, but make sure that one aliases the other, > e.g. so that (if your SIMD width is 16) VGPR 20 overlaps SGPR 320, > 321….335. So you can have...