search for: vfp4

...enabled by a specific option. For a particular CPU for example. 'auto' FPU value (Renato) ================ >> I'd have assumed -mfpu is already "auto" by default. Or is this to >> just override a previous option? >> >> ex: clang -mcpu cortex-a8 -mfpu vfp4 -mfpu auto -> defaults back to VFP3. I don't see any reference to this in the code or the docs, and clang something similair: ./clang --target=arm-arm-none-eabi -mcpu=cortex-a8 -mfpu=vfp4 -mfpu=auto -c /tmp/test.c clang-8: error: the clang compiler does not support '-mfpu=auto' May...

Hi Anitha, Thanks for your answer but -mcpu=cortex-a9 -mattr=+vfp4 doesn' t enable fused mac generation for me. I would like just to understand why -mtriple=armv7-eabi enables it while -mcpu=cortex-a9 seems to disable it ? Seb > -----Original Message----- > From: Anitha Boyapati [mailto:anitha.boyapati at gmail.com] > Sent: Thursday, November 08, 20...

...o be able to see the name Rameses and > map this to the correct John Smith (or at least someone very much like him). > This is the gist of what ARMTargetParser is/was doing. A good example is "krait", a CPU design from Qualcomm. Krait used to be mapped to Cortex-A15 because it has VFP4 and HDIV, but architecturally, it is a lot closer to a Cortex-A9 than an A15. So assuming that Krait == A15 means making a lot of bad optimisation decisions in the back-end, and the code performed poorly. This year we made the change, so that Krait == A9+HDIV+VFP4, but neither the triple, nor the...

...ultiply-add, it's a multiply followed by an add and has different latency as well as precision. On Thu, Nov 8, 2012 at 4:57 AM, Sebastien DELDON-GNB <sebastien.deldon at st.com<mailto:sebastien.deldon at st.com>> wrote: Hi Anitha, Thanks for your answer but -mcpu=cortex-a9 -mattr=+vfp4 doesn' t enable fused mac generation for me. I would like just to understand why -mtriple=armv7-eabi enables it while -mcpu=cortex-a9 seems to disable it ? Seb > -----Original Message----- > From: Anitha Boyapati [mailto:anitha.boyapati at gmail.com<mailto:anitha.boyapati at gmail.co...

...VMLA isn't a fused multiply-add, it's a multiply followed by an add and has different latency as well as precision. On Thu, Nov 8, 2012 at 4:57 AM, Sebastien DELDON-GNB < sebastien.deldon at st.com> wrote: > Hi Anitha, > > Thanks for your answer but -mcpu=cortex-a9 -mattr=+vfp4 doesn' t enable > fused mac generation for me. > I would like just to understand why -mtriple=armv7-eabi enables it while > -mcpu=cortex-a9 seems to disable it ? > > Seb > > > -----Original Message----- > > From: Anitha Boyapati [mailto:anitha.boyapati at gmail.com...

Hi all, I've a .ll code that use double precision fmul/fadd or fmul/fsub. When I compile it using llc -mcpu=cortex-a9 I couldn't get vmla/vmls generated even using -fp-contract=fast, but when I use option -mtriple=armv7-eabi instead of -mcpu=cortex-a9 fused mac are generated. Can someone explain me why ? Thanks for your answers Seb -------------- next part -------------- An HTML

...n I > compile it using llc –mcpu=cortex-a9 I couldn’t get vmla/vmls generated even > using –fp-contract=fast, but when I use option –mtriple=armv7-eabi instead > of –mcpu=cortex-a9 fused mac are generated. Can someone explain me why ? > Perhaps you need to use some attributes. -mattr=+vfp4 Check fusedMAC.ll from ARM codegen tests. -- Anitha

...add and has different latency as well as precision. > > > > > > > > On Thu, Nov 8, 2012 at 4:57 AM, Sebastien DELDON-GNB > > <sebastien.deldon at st.com> wrote: > > > > Hi Anitha, > > > > Thanks for your answer but -mcpu=cortex-a9 -mattr=+vfp4 doesn' t > > enable fused mac generation for me. > > I would like just to understand why -mtriple=armv7-eabi enables it > > while > > -mcpu=cortex-a9 seems to disable it ? > > > > Seb > > > > > >> -----Original Message----- > >>...

...-add, it's a multiply followed by an add and has > different latency as well as precision. > > > > On Thu, Nov 8, 2012 at 4:57 AM, Sebastien DELDON-GNB > <sebastien.deldon at st.com> wrote: > > Hi Anitha, > > Thanks for your answer but -mcpu=cortex-a9 -mattr=+vfp4 doesn' t enable > fused mac generation for me. > I would like just to understand why -mtriple=armv7-eabi enables it while > -mcpu=cortex-a9 seems to disable it ? > > Seb > > >> -----Original Message----- >> From: Anitha Boyapati [mailto:anitha.boyapati at gmail....

...cision. > > > > > > > > > > > > On Thu, Nov 8, 2012 at 4:57 AM, Sebastien DELDON-GNB > > > <sebastien.deldon at st.com> wrote: > > > > > > Hi Anitha, > > > > > > Thanks for your answer but -mcpu=cortex-a9 -mattr=+vfp4 doesn' t > > > enable fused mac generation for me. > > > I would like just to understand why -mtriple=armv7-eabi enables it > > > while > > > -mcpu=cortex-a9 seems to disable it ? > > > > > > Seb > > > > > > > > >&...

...t quite accurate. It’s not A9+HDIV+VFP. It uses the A9 scheduling model, yes, but has its own completely distinct list of sub target features and such: Well, this is the target description in the TableGen files, and not exactly what I was talking about. when available, A9 has VFP3, while Krait has VFP4. Which brings the other side of the discussion, around the TargetParser, that the information in Clang is completely disconnected from the TableGen descriptions, but it's not relevant to the discussion. > Having the triple, or anything else outside this level of implementation details, re...

...precision. > > > > > > > > On Thu, Nov 8, 2012 at 4:57 AM, Sebastien DELDON-GNB > > <sebastien.deldon at st.com<mailto:sebastien.deldon at st.com>> wrote: > > > > Hi Anitha, > > > > Thanks for your answer but -mcpu=cortex-a9 -mattr=+vfp4 doesn' t > > enable fused mac generation for me. > > I would like just to understand why -mtriple=armv7-eabi enables it > > while > > -mcpu=cortex-a9 seems to disable it ? > > > > Seb > > > > > >> -----Original Message----- > >>...

...pic -pic-level 1 -mthread-model posix -mdisable-fp-elim -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu generic -target-feature +soft-float-abi -target-feature -fp-only-sp -target-feature +d16 -target-feature +vfp3 -target-feature -fp16 -target-feature -vfp4 -target-feature -fp-armv8 -target-feature -neon -target-feature -crypto -target-abi aapcs-linux -mfloat-abi soft -fallow-half-arguments-and-returns -dwarf-column-info -debug-info-kind=limited -dwarf-version=4 -debugger-tuning=gdb -target-linker-version 351.8 -ffunction-sections -coverage-notes-file...

Hi, Below is a document detailing changes we'd like to make to Clang/LLVM to improve the usability of the target options for ARM and AArch64. To keep things simple the proposed changes are listed at the start and you can find the supporting examples at the end of the document. I look forward to your feedback. Thanks, David Spickett. RFC New Clang target feature selection options for

...hread-model posix > -mdisable-fp-elim -fmath-errno -masm-verbose -mconstructor-aliases > -munwind-tables -fuse-init-array -target-cpu generic -target-feature > +soft-float-abi -target-feature -fp-only-sp -target-feature +d16 > -target-feature +vfp3 -target-feature -fp16 -target-feature -vfp4 > -target-feature -fp-armv8 -target-feature -neon -target-feature -crypto > -target-abi aapcs-linux -mfloat-abi soft -fallow-half-arguments-and-returns > -dwarf-column-info -debug-info-kind=limited -dwarf-version=4 > -debugger-tuning=gdb -target-linker-version 351.8 -ffunction-sections...

...-------------------- The HPR registerclass and f16 type are added as a legal type when: - FullFP16 is enabled, which means support for the Armv8.2-A FP16 instructions, - FP16 is enabled, which means support for the f16 <-> f32 conversion instructions, which are a VFP3 extension and part of VFP4. It's obvious why f16 is legal for the former case, but the latter is perhaps the more interesting/instrusive change. Making fp16 legal for FP16, results in f16 LOADs/STOREs while we don't have instructions for them. So the approach is to custom lower f16 LOAD/STORE nodes (see next section...

> > The Triple object will remain unchanged. > > The Tuple will be the API to handle getting/setting parameters > depending on the Triple, compiler flags, attributes, etc. > > This part doesn't seem obvious from the direction the patches are going. > There will be no string representation of all options, as that would > be impossible, or at least, highly