search for: vfp3

Thanks, that helps a lot. > All chips (to date) with NEON have VFP3, so it's safe to assume that a -mfpu=neon will have VFP3, so all the decisions > about code generated for VFP3 can safely be assumed by targets with NEON. Just to confirm my understanding, can I correctly say in general that the llc code generator might blur distinctions between NEON and...

On May 27, 2011, at 10:49 AM, David Dunkle wrote: > Thanks, that helps a lot. > >> All chips (to date) with NEON have VFP3, so it's safe to assume that a > -mfpu=neon will have VFP3, so all the decisions >> about code generated for VFP3 can safely be assumed by targets with > NEON. > > Just to confirm my understanding, can I correctly say in general that > the llc code generator might blur di...

On 27 May 2011 02:04, David Dunkle <ddunkle at arxan.com> wrote: > In all cases, I get code that looks pretty very the same; its like what > is below. However, I am expecting to see instruction level differences > between the vfp3 and neon versions. When I do the same with gcc 4.2 I do > see differences in the generated code. Hi David, You could see different instructions (as gcc does, you say), but it's not necessary. Your example has only floating point arithmetic, which both VFP3 and NEON can do, so the final as...

...1, float f2, float f3) { float f4 = f1 * f2; if (f4 > f3) printf("%f\n",f2); else printf("%f\n",f3); } I have tried compiling with: 1. -mfloat-abi=softfp and -mfpu=neon 2. -mfloat-abi=hard and -mfpu=neon 3. -mfloat-abi=softfp and -mfpu=vfp3 4. -mfloat-abi=hard and -mfpu=vfp3 When I use --emit-llvm -c flags to generate bitcode, and then use llc to generate ARM assembler, I have tried supplying these flag variations to llc: 5. llc -mattr=+neon 6. llc -mattr=+vfp3 I am building for armv7-a. In all cases, I get code that...

On 27 May 2011 19:47, Jim Grosbach <grosbach at apple.com> wrote: > Not exactly. The distinction is clear, it's just not expressed as an > either/or question. Specifically, the code generator considers NEON to be a > proper superset of VFP3. So if it has only VFP3, that's all it will use. If > it has NEON, it assumes it also has VFP3 and can use either. Indeed. > There's not, > currently, a way to say "use only NEON instructions; don't generate any > VFP3." Which would be advantageous on some case...

...ools like llvm-mc, in which case >you can use the -mattr=+vfpv3 flag to enable it. This applies to other >subtarget features defined in ARM.td as well. > >Cheers, >Amara > >On 23 June 2014 11:27, Damanjit Singh <dsingh at adobe.com> wrote: >> How can I ensure use of VFP3 via LLVM target options? I am currently >>using >> thumbv7-windows-msvc as the target triple and default set of >> llvm::TargetOptions. >> >> Thanks, >> Daman >> >> _______________________________________________ >> LLVM Developers mailing list...

How can I ensure use of VFP3 via LLVM target options? I am currently using thumbv7-windows-msvc as the target triple and default set of llvm::TargetOptions. Thanks, Daman -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140623/bdf36cce/a...

Hello, I'm trying to convince llc to compile into thumb2 ISA on ARMv7. I'm using: -march=thumb -mattr=v7,thumb2,vfp3 but llc complains about this with: llc: error: invalid target 'thumb -mattr=v7,thumb2,vfp3' I'm using LLVM from Aug 29 2011. To me the set of options looks sane so I'd like to ask what's wrong with this. Thanks! Karel

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Hi Karel, It actually looks like the argument parser has parsed "thumb -mattr=v7,thumb2,vfp3" as the full argument to "-march=". Strange. The easiest way to get what you want is probably "-mtriple thumbv7--". v7 has Thumb2 enabled and VFPv3 (along with NEON) by default. Cheers, James ________________________________________ From: llvmdev-bounces at cs.uiuc.edu [...

Thanks andrew for the answer. I would like to generate code for Cortex-A9 that don't use neon for fp computation but vfpv3 -d16. I've tried some combination of -mattr=+neon,-neonfp,+vfp3,+d16 but couldn't get ".fpu vfpv3-d16" directive generated in assembly file. Do you know how to make it happen ? Best Regards Seb From: Andrew Trick [mailto:atrick at apple.com] Sent: Saturday, July 28, 2012 2:46 AM To: Sebastien DELDON-GNB Cc: llvmdev at cs.uiuc.edu Subject: Re: [L...

...rticular CPU for example. 'auto' FPU value (Renato) ================ >> I'd have assumed -mfpu is already "auto" by default. Or is this to >> just override a previous option? >> >> ex: clang -mcpu cortex-a8 -mfpu vfp4 -mfpu auto -> defaults back to VFP3. I don't see any reference to this in the code or the docs, and clang something similair: ./clang --target=arm-arm-none-eabi -mcpu=cortex-a8 -mfpu=vfp4 -mfpu=auto -c /tmp/test.c clang-8: error: the clang compiler does not support '-mfpu=auto' Maybe I'm missing something. ACLE mac...

Hi all, I'm hitting a segfault in llc when trying to build GHC: http://sprunge.us/ZVGB. What is the best way to debug this? I'm able to bump to 3.8.1 if needed, but GHC tends to break when updating major versions due to IR incompatibilities. Thanks, Shea -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size:

...p;): Assertion `(isImpReg || !OperandsComplete()) && "Trying to add an operand to a machine instr that is already done!"' failed. Stack dump: 0. Program arguments: llc -O3 -relocation-model=static /tmp/ghc12607_0/ghc12607_0.bc -o /tmp/ghc12607_0/ghc12607_0.lm_s -mattr=+v7,+vfp3 1. Running pass 'Function Pass Manager' on module '/tmp/ghc12607_0/ghc12607_0.bc'. 2. Running pass 'ARM load / store optimization pass' on function '@s51E_info' Aborted FYI: Stephen Blackheath enhanced LLVM to support custom GHC calling convention on ARM and I...

...ssertion `(isImpReg || !OperandsComplete()) && "Trying to add an operand to a machine instr that is already done!"' failed. > Stack dump: > 0. Program arguments: llc -O3 -relocation-model=static /tmp/ghc12607_0/ghc12607_0.bc -o /tmp/ghc12607_0/ghc12607_0.lm_s -mattr=+v7,+vfp3 > 1. Running pass 'Function Pass Manager' on module '/tmp/ghc12607_0/ghc12607_0.bc'. > 2. Running pass 'ARM load / store optimization pass' on function '@s51E_info' > Aborted > > FYI: Stephen Blackheath enhanced LLVM to support custom GHC calling conv...

...nts: > /nix/store/izlawmnrzpk5sbr62c757cxay0kdlgam-llvm-3.8.0/bin/llc -O3 > -relocation-model=dynamic-no-pic > /private/tmp/nix-build-ghc-8.1.201601019.drv-3/ghc37608_0/ghc_5.bc -o > /private/tmp/nix-build-ghc-8.1.201601019.drv-3/ghc37608_0/ghc_6.lm_s > --enable-tbaa=true -mattr=+v7,+vfp3 > [...] > 1. Running pass 'Function Pass Manager' on module > '/private/tmp/nix-build-ghc-8.1.201601019.drv-3/ghc37608_0/ghc_5.bc'. > 2. Running pass 'Prologue/Epilogue Insertion & Frame Finalization' on > function '@"stg_unmaskAsyncExceptionszh_r...

...ngv/DRAGONEGG_DIR/src/Backend.cpp: In function ‘void CreateTargetMachine(const string&)’: /gaia/class/student/seerangv/DRAGONEGG_DIR/include/arm/dragonegg/Target.h:254:37: error: no matching function for call to ‘llvm::SubtargetFeatures::AddFeature(const char [5], bool)’ F.AddFeature("vfp3", TARGET_VFP3); \ ^ /gaia/class/student/seerangv/DRAGONEGG_DIR/src/Backend.cpp:464:3: note: in expansion of macro ‘LLVM_SET_SUBTARGET_FEATURES’ LLVM_SET_SUBTARGET_FEATURES(CPU, Features); ^ /gaia/class/student/seerangv/DRAGONEGG_DIR/include/arm/dr...

...`(isImpReg || !OperandsComplete())&& "Trying to add an operand to a machine instr that is already done!"' failed. >> Stack dump: >> 0. Program arguments: llc -O3 -relocation-model=static /tmp/ghc12607_0/ghc12607_0.bc -o /tmp/ghc12607_0/ghc12607_0.lm_s -mattr=+v7,+vfp3 >> 1. Running pass 'Function Pass Manager' on module '/tmp/ghc12607_0/ghc12607_0.bc'. >> 2. Running pass 'ARM load / store optimization pass' on function '@s51E_info' >> Aborted >> >> FYI: Stephen Blackheath enhanced LLVM to support cust...

...wrote: > That’s not quite accurate. It’s not A9+HDIV+VFP. It uses the A9 scheduling model, yes, but has its own completely distinct list of sub target features and such: Well, this is the target description in the TableGen files, and not exactly what I was talking about. when available, A9 has VFP3, while Krait has VFP4. Which brings the other side of the discussion, around the TargetParser, that the information in Clang is completely disconnected from the TableGen descriptions, but it's not relevant to the discussion. > Having the triple, or anything else outside this level of impl...

...p_le/bin/arm_v7_vfp_le-as --with-ld=/home/arm_v7_vfp_le/bin/arm_v7_vfp_le-ld --enable-checking=release --disable-multilib --enable-llvm=/home/Desktop/Sanjeev/LLVM/llvm-2.7 --enable-clocale=gnu --with-cpu=cortex-a8 --with-interwork --with-arch=armv7-a --with-mode=arm --with-tune=cortex-a8 --with-fpu=vfp3 --disable-bootstrap --disable-libmudflap --disable-libssp Thread model: posix gcc version 4.2.1 (Based on Apple Inc. build 5658) (LLVM build) These are the steps how I'm building library on ARM+llvm. generated .a is linked with other targets built with native arm compiler. g++-cross -flto...