search for: vfn

...\ + return sprintf(buf, "%d\n", iov->field); \ +} + +iov_config_attr(is_enabled); +iov_config_attr(totalvfs); +iov_config_attr(initialvfs); +iov_config_attr(numvfs); + +struct vf_entry { + int vfn; + struct kobject kobj; + struct pci_iov *iov; + struct iov_attr *attr; + char name[VF_NAME_LEN]; + char (*param)[PCI_IOV_PARAM_LEN]; +}; + +static ssize_t iov_attr_show(struct kobject *kobj, + struct attribute *attr, char *buf) +{ + struct iov_attr...

...ractice? Initially Pete had to thread special handling for this intrinsic everywhere till instruction selection. I changed the semantic of the intrinsic to be completely opaque, the codegen I have looks like: %vtable = load void (%struct.Derived2*)**, void (%struct.Derived2*)*** %3, align 8 %vfn_ptr = getelementptr inbounds void (%struct.Derived2*)*, void (%struct.Derived2*)** %vtable, i64 1 %vfn = load void (%struct.Derived2*)*, void (%struct.Derived2*)** %vfn_ptr, align 8 call void %vfn(%struct.Derived2* %2) to: %vtable = load void (%struct.Derived2*)**, void (%struct.Derived2*)*...

...\ + return sprintf(buf, "%d\n", iov->field); \ +} + +iov_config_attr(is_enabled); +iov_config_attr(totalvfs); +iov_config_attr(initialvfs); +iov_config_attr(numvfs); + +struct vf_entry { + int vfn; + struct kobject kobj; + struct pci_iov *iov; + struct iov_attr *attr; + char name[VF_NAME_LEN]; + char (*param)[PCI_IOV_PARAM_LEN]; +}; + +static ssize_t iov_attr_show(struct kobject *kobj, + struct attribute *attr, char *buf) +{ + struct iov_attr...

...\ + return sprintf(buf, "%d\n", iov->field); \ +} + +iov_config_attr(is_enabled); +iov_config_attr(totalvfs); +iov_config_attr(initialvfs); +iov_config_attr(numvfs); + +struct vf_entry { + int vfn; + struct kobject kobj; + struct pci_iov *iov; + struct iov_attr *attr; + char name[VF_NAME_LEN]; + char (*param)[PCI_IOV_PARAM_LEN]; +}; + +static ssize_t iov_attr_show(struct kobject *kobj, + struct attribute *attr, char *buf) +{ + struct iov_attr...

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. [PATCH 1/8 v4] PCI: define PCI resource names in a 'enum' [PATCH 2/8 v4] PCI: export __pci_read_base

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. [PATCH 1/8 v4] PCI: define PCI resource names in a 'enum' [PATCH 2/8 v4] PCI: export __pci_read_base

...owing to be considered a newly formed valid pointer. BTW, Richard came up with a wonderful example. What do you make of this?: char alignas(A, B) buffer[max(sizeof(A), sizeof(B))]; A *a = reinterpret_cast<A*>(buffer); B *b = reinterpret_cast<B*>(buffer); new(buffer) A; a->vfn(); new(buffer) B; b->vfn(); Valid? Nick -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130509/06228a9a/attachment.html>

Virtual call translates into IR like this: %0 = bitcast %class.A* %call to i32 (%class.A*, i32)*** %vtable = load i32 (%class.A*, i32)*** %0 %vfn = getelementptr inbounds i32 (%class.A*, i32)** %vtable, i64 0 %1 = load i32 (%class.A*, i32)** %vfn Is it possible to map pair [StructType, methodIndex(i64 0 in example)] into Function? Yours sincerely, Kadysev Mikhail -------------- next part -------------- An HTML attachment was scrubbed....

...nters these days? > BTW, Richard came up with a wonderful example. What do you make of this?: > > char alignas(A, B) buffer[max(sizeof(A), sizeof(B))]; > A *a = reinterpret_cast<A*>(buffer); > B *b = reinterpret_cast<B*>(buffer); > new(buffer) A; > a->vfn(); > new(buffer) B; > b->vfn(); > > Valid? Let's answer a simpler question. Why is this valid? A *a = reinterpret_cast<A*>(buffer); new(buffer) A; a->vfn(); My initial interpretation is that the initial value of 'a' is a type-punned pointer t...

...lid pointer. > > BTW, Richard came up with a wonderful example. What do you make of this?: > > char alignas(A, B) buffer[max(sizeof(A), sizeof(B))]; > A *a = reinterpret_cast<A*>(buffer); > B *b = reinterpret_cast<B*>(buffer); > new(buffer) A; > a->vfn(); > new(buffer) B; > b->vfn(); > > Valid? > > Nick > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev -----------...

Hi, I just thought about another use case: VTable compression. If you know that an entry in the Vtable is never used, just remove it! I’d hope we could even eliminate some unused virtual functions from the final binary. — Mehdi > On Jan 27, 2016, at 10:29 PM, Mehdi Amini via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi Peter, > > Pete (Cooper, CC'ed) had a

...ndpoints is zero. With ARI enabled, an Endpoint can have up to 256 +functions by using device number in conjunction with function number to +indicate a function in the device. This is almost transparent to the Linux +kernel because the Linux kernel still can use 8-bit bus number field plus +8-bit devfn number field to locate a function. ARI is managed via the ARI +Forwarding bit in the Device Capabilities 2 register of the PCI Express +Capability on the Root Port or the Downstream Port and a new ARI Capability +on the Endpoint. + + +2. User Guide + +2.1 How can I manage SR-IOV + +If a device supp...

...ndpoints is zero. With ARI enabled, an Endpoint can have up to 256 +functions by using device number in conjunction with function number to +indicate a function in the device. This is almost transparent to the Linux +kernel because the Linux kernel still can use 8-bit bus number field plus +8-bit devfn number field to locate a function. ARI is managed via the ARI +Forwarding bit in the Device Capabilities 2 register of the PCI Express +Capability on the Root Port or the Downstream Port and a new ARI Capability +on the Endpoint. + + +2. User Guide + +2.1 How can I manage SR-IOV + +If a device supp...

...s.B* %obj2) #4 %0 = bitcast %class.A* %obj1 to %class.Base* store %class.Base* %0, %class.Base** %C, align 8 %1 = load %class.Base*, %class.Base** %C, align 8 %2 = bitcast %class.Base* %1 to void (%class.Base*)*** %vtable = load void (%class.Base*)**, void (%class.Base*)*** %2, align 8 %vfn = getelementptr inbounds void (%class.Base*)*, void (%class.Base*)** %vtable, i64 0 %3 = load void (%class.Base*)*, void (%class.Base*)** %vfn, align 8 call void %3(%class.Base* %1) ret i32 0 } Related C++ code class Base { public: virtual void hello(); }; class A: public Bas...

Dear Mailing List, This might sound unconventional, but I am trying to access a C++ objects vtable to pass as an argument to a function call for a library function I created. Creating & inserting a function call at the correct location in LLVM is done. I have learned that C++ objects are represented as struct types. But I'm just not quite sure how to get at the vtable pointer within,

On May 9, 2013, at 6:34 PM, Nick Lewycky <nlewycky at google.com> wrote: > I'm looking into how we can improve devirtualization in clang, and there a language in C++ feature I'd like to take advantage of which would let us perform elimination of more vptr loads. In this code: > > Cls *p = new Cls; > p->virtual_method1(); > p->method_changing_vptr(); //

...lt;div><div>Alias Set Tracker: 4 alias sets for 7 pointer values.</div><div> AliasSet[0x93a80b8, 1] must alias, Mod Pointers: (i32* %retval, 4)</div><div> AliasSet[0x93a80e0, 4] may alias, Mod/Ref Pointers: (void (%class.B*)*** %4, 4), (void (%class.B*)** %vfn, 4), (void (%class.B*)*** %9, 4), (void (%class.B*)** %vfn2, 4)</div><div> 6 Unknown instructions: i8* %call, void <badref>, void <badref>, void <badref>, void <badref>, void <badref></div><div><b><font color="#ff0000">...

I'm looking into how we can improve devirtualization in clang, and there a language in C++ feature I'd like to take advantage of which would let us perform elimination of more vptr loads. In this code: Cls *p = new Cls; p->virtual_method1(); p->method_changing_vptr(); // uses placement new to legally change the vptr p->virtual_method2(); // invalid! Cls *q = p;

..._vifscript = NULL; @@ -103,8 +106,9 @@ int main(int argc, char **argv) char *config_file; void *config_data = 0; int config_len = 0; + const char *locks[] = XEND_LOCK; - while ((opt = getopt(argc, argv, "+vN")) >= 0) { + while ((opt = getopt(argc, argv, "+vfN")) >= 0) { switch (opt) { case ''v'': if (minmsglevel > 0) minmsglevel--; @@ -112,6 +116,9 @@ int main(int argc, char **argv) case ''N'': dryrun_only = 1; break; + case ''f...

..... .. ..$ y : num [1:31837] 43136 43126 43123 43125 42709 ... .. .. ..$ wz: num [1:31837] -101.1 -94.9 -93.3 -94.5 30.8 ... .. ..$ has.intercept: int 1 .. ..$ beta : num(0) .. ..$ nmax : num 500 .. ..$ maxdist : num Inf .. ..$ dummy : logi FALSE .. ..$ vfn : int 1 .. ..$ weights : NULL $ model:List of 1 ..$ rv:Classes variogram.model and `data.frame': 1 obs. of 9 variables: .. ..$ model: Factor w/ 16 levels "Nug","Exp","Sph",..: 5 .. ..$ psill: num 1652 .. ..$ range: num 126 .. ..$ ka...