search for: vext

...lanes */ + "vshll.s16 q7, d0, %[SIGSHIFT];\n" + "vshll.s16 q8, d1, %[SIGSHIFT];\n" + "vshll.s16 q9, d2, %[SIGSHIFT];\n" + "vshll.s16 q10, d3, %[SIGSHIFT];\n" + + /* Make previous samples vector for MAC in q5, q6 lanes */ + "vext.16 q5, q5, q0, #7;\n" + "vext.16 q6, q0, q1, #7;\n" + + /* Doing 16 samples filtering at a time */ + "vmlal.s16 q7, d8, d10;\n" + "vmlal.s16 q8, d8, d11;\n" + "vmlal.s16 q9, d8, d12;\n" + "vmlal.s16 q10, d8, d13;\n&quot...

...lanes */ + "vshll.s16 q7, d0, %[SIGSHIFT];\n" + "vshll.s16 q8, d1, %[SIGSHIFT];\n" + "vshll.s16 q9, d2, %[SIGSHIFT];\n" + "vshll.s16 q10, d3, %[SIGSHIFT];\n" + + /* Make previous samples vector for MAC in q5, q6 lanes */ + "vext.16 q5, q5, q0, #7;\n" + "vext.16 q6, q0, q1, #7;\n" + + /* Doing 16 samples filtering at a time */ + "vmlal.s16 q7, d8, d10;\n" + "vmlal.s16 q8, d8, d11;\n" + "vmlal.s16 q9, d8, d12;\n" + "vmlal.s16 q10, d8, d13;\n&quot...

Andrew Trick <atrick at apple.com> writes: > David was asking for a post-register-rewrite analysis, which I think > is a totally different problem and best implemented separately by each > target. The target knows best which register units are overwritten or > preserved by an operation. We try to fake it with > undef/implicit-use/implicit-def, but it isn't reliable.

On Apr 16, 2013, at 10:27 AM, John Criswell <criswell at illinois.edu> wrote: > On 4/16/13 11:30 AM, dag at cray.com wrote: >> Is there a traditional dataflow algorithm buried in LLVM somewhere? I >> need to be able to do some very late transformations (after regalloc) >> and we aren't in SSA anymore. I will need a dataflow analysis to ensure >> correctness.

Hello, I have a minimal testcase which crashes RegisterCoalescer in my out-of-tree target. It only crashes in Debug builds of llc---not in Release builds. Also, interesting to note that the x86 backend lowers this same testcase successfully. I did a quick search of bugs.llvm.org and found no matches. This implies that the problem is in my backend and/or how my backend interacts with

Hi, We are now about halfway between the 3.4 and 3.5 releases, and I would like to start preparing for a 3.4.1 release. Here is my proposed release schedule: Mar 26 - April 9: Identify and backport additional bug fixes to the 3.4 branch. April 9 - April 18: Testing Phase April 18: 3.4.1 Release How you can help: - If you have any bug fixes you think should be included to 3.4.1, send me an