search for: vexpand

Hi all, AVX-512 ISA introduces new vector instructions VCOMPRESS and VEXPAND in order to allow vectorization of the following loops with two specific types of cross-iteration dependencies: Compress: for (int i=0; i<N; ++i) If (t[i]) *A++ = expr; Expand: for (i=0; i<N; ++i) If (t[i]) X[i] = *A++;...

...2, V1, V2, Mask, Subtarget, DAG)) return Rotate; // Assume that a single SHUFPS is faster than using a permv shuffle. // If some CPU is harmed by the domain switch, we can fix it in a later pass. // If we have AVX512F support, we can use VEXPAND. if (SDValue V = lowerVectorShuffleToEXPAND(DL, MVT::v64i32, Zeroable, Mask, V1, V2, DAG, Subtarget)) return V; return lowerVectorShuffleWithPERMV(DL, MVT::v64i32, Mask, V1, V2, DAG); } static SDValue lowerV32I64VectorShuffle(const SDLoc &...

...av Rotem" |<nadav.rotem at me.com> |> Sent: Monday, September 19, 2016 1:37:02 AM |> Subject: RFC: New intrinsics masked.expandload and |> masked.compressstore |> |> |> Hi all, |> |> AVX-512 ISA introduces new vector instructions VCOMPRESS and |VEXPAND |> in order to allow vectorization of the following loops with two |> specific types of cross-iteration dependencies: |> |> Compress: |> for (int i=0; i<N; ++i) |> If (t[i]) |> *A++ = expr; |> |> Expand: |> for (i=0; i<N; ++i) |> If (t[i]...

...y, September 19, 2016 1:37:02 AM |> |> Subject: RFC: New intrinsics masked.expandload and |> |> masked.compressstore |> |> |> |> |> |> Hi all, |> |> |> |> AVX-512 ISA introduces new vector instructions VCOMPRESS |and |> |VEXPAND |> |> in order to allow vectorization of the following loops with two |> |> specific types of cross-iteration dependencies: |> |> |> |> Compress: |> |> for (int i=0; i<N; ++i) |> |> If (t[i]) |> |> *A++ = expr; |> |>...