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- we used the C4/C5 (first prefix) byte instead of the apparent ModR/M one as the second prefix byte - early decoding normalized vex.reg, thus corrupting it for the main consumer (copy_REX_VEX()), resulting in #UD on the two-operand instructions we emulate Also add respective test cases to the testing utility plus - fix get_fpu() (the fall-through order was inverted) - add cpu_has_avx2, even if it''s currently unuse...

On Thu, 4 Aug 2016 14:03:39 +0100 Nabeel <nabeelshikder at gmail.com> wrote: > I should add, a password is *always* asked if a password has been set. > There isn't a way to bypass that. Then something is wrong. http://darcy.vex.net/star98.mp3 -- D'Arcy J.M. Cain System Administrator, Vex.Net http://www.Vex.Net/ IM:darcy at Vex.Net VoIP: sip:darcy at Vex.Net

...struction set was introduced in X86 it included additional 32 registers of 512bit size each ZMM0 - ZMM31, as well as additional 16 XMM registers XMM16-XMM31 and 16 YMM registers YMM16-YMM31. In order to encode the new registers of 16-31 and the additional instructions, a new encoding prefix called EVEX, which extends the existing VEX encoding, was introduced as shown below: The EVEX encoding format: EVEX Opcode ModR/M [SIB] [Disp32] / [Disp8*N] [Immediate] # of bytes: 4 1 1 1 4 / 1 1 The existing VEX encoding format: [VEX] OPCODE ModR/M...

...----- Opcode - Single byte value indicating the opcode within the various X86 opcode maps. For most instructions this the value between prefixes and the ModRM byte. Form - Classifies how operands are encoded into the various fields that encode operands, i.e. modrm.reg, modrm.rm, vex.vvvv, rex.r, rex.x, rex.b, etc. See format list below. ImmT - Determines the size of the immediate, if any at the end of the instruction. OpSize - Used to inciate instructions that need a 0x66 operand size prefix to encode 16-bit operands in 32 mode or 32-bit operands in 16-bit...

On Thu, Nov 8, 2012 at 1:34 AM, Anitha Boyapati <anitha.boyapati at gmail.com>wrote: ... > > I actually have confusion in mapping the role of vex_w during > instruction selection. For the moment, lets just consider vex_w and > not memop. > > [1]. What does " def rr : FMA4<>, VEX_W" mean? As per tablegen > description, "rr" now inherits FMA4 and VEX_W. However VEX_W is not a > class, it is an enumer...

...n 8 November 2012 11:12, Cameron McInally <cameron.mcinally at nyu.edu> wrote: > On Wed, Nov 7, 2012 at 10:52 PM, Anitha Boyapati <anitha.boyapati at gmail.com> > wrote: > ... >> >> For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and >> "MemOp4" like those of "rm" or "rr" ? > > > Hey Anitha, > > The VEX.W bit is used to denote operand order. In other words, this bit > allows for a memop to be used as either the second or third source operand > of an FMA instru...

I am attempting to create an instruction which takes a single 64-bit immediate. This doesn't seem like a thing that would exist already (because who needs an instruction which just takes an immediate?) How might I implement this easily? Perhaps I could use a format which encodes a register, which is then unused? Thanks for the help. Gus -------------- next part -------------- An HTML

I would like a command line option to disable this optimization. That way tests can still verify that EVEX instructions came out of isel by using -show-mc-encoding. On Wed, Nov 23, 2016 at 5:01 AM Hal Finkel via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > ------------------------------ > > *From: *"Gadi via llvm-dev Haber" <llvm-dev at lists.llvm.org> > *To:...

Hi guys, I just upgraded our JIT system to use llvm 3.5 and noticed one big change in our generated code: we don't see any non-destructive VEX prefix instructions being emitted any more (vmulsd xmm0, xmm1, blah) etc. It's long been on my list of things to investigate anyway as I noticed llvm didn't emit VZEROUPPER calls either, so I supposed it might not be a bad thing to disable vex. That being said, try as I might I can't...

> I would like a command line option to disable this optimization. That way tests can still verify that EVEX instructions came out of isel by using -show-mc-encoding. I think that keeping tests compatibility is not a reason for an additional “llc” flag. We check encoding in test/MC/X86 dir. Is there any option to report-out from llc in non-debug mode? It should be an option to control internals of llc p...

...=> n,Dial(SIP/4164251212,30) same => n,VoiceMail(4164251212 at LocalSets,u) same => n,Hangup() I can post any other log or config excerpts if someone thinks that they are relevant but all of this was working under 11.10.2. Thanks. -- D'Arcy J.M. Cain System Administrator, Vex.Net http://www.Vex.Net/ IM:darcy at Vex.Net VoIP: sip:darcy at Vex.Net

...up other code: - keep track of REP prefixes in only one variable - use REX_W in a few more places (instead of a literal number) Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -304,6 +304,10 @@ union vex { ptr[1] = rex | REX_PREFIX; \ } while (0) +#define rep_prefix() (vex.pfx >= vex_f3) +#define repe_prefix() (vex.pfx == vex_f3) +#define repne_prefix() (vex.pfx == vex_f2) + /* Type, address-of, and value of an instruction''s operand. */ struct operand { enum { OP_R...

...TX-TGD220 and mine is a TX-TGD-212. The difference is mainly that his has a built in answering machine. As I said, no one else is having the issue. One person has a horrible connection with voice drops all the time but the touch tones still work. I have made two files available. http://darcy.vex.net/Bishop.ogg is an OGG file of the sound that it makes at the receiving end and the other at http://darcy.vex.net/Bishop.png is a picture of the wave form. I had the user think "one Mississippi" etc. and alternately press and release three different buttons. I recorded off my SIP...

On Wed, Nov 7, 2012 at 10:52 PM, Anitha Boyapati <anitha.boyapati at gmail.com>wrote: ... > For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and > "MemOp4" like those of "rm" or "rr" ? > Hey Anitha, The VEX.W bit is used to denote operand order. In other words, this bit allows for a memop to be used as either the second or third source operand of an FMA instruction, offering greater flexibil...

...or core dump. I have improved the situation by expanding my intrusion detection but it still stops every few days or so. I have a cron job that tests for it and restarts it when necessary. Anyone else have experience on non-Linux systems? Cheers. -- D'Arcy J.M. Cain System Administrator, Vex.Net http://www.Vex.Net/ IM:darcy at Vex.Net VoIP: sip:darcy at Vex.Net

...let us know. From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Hal Finkel via llvm-dev Sent: Wednesday, November 23, 2016 15:01 To: Haber, Gadi <gadi.haber at intel.com> Cc: llvm-dev at lists.llvm.org Subject: Re: [llvm-dev] RFC: code size reduction in X86 by replacing EVEX with VEX encoding ________________________________ From: "Gadi via llvm-dev Haber" <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> To: llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org> Sent: Wednesday, November 23, 2016 5:50:42 AM Subject: [...

Hi, A question from r162999 changes: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFMA.td?r1=162999&r2=162998&pathrev=162999 For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and "MemOp4" like those of "rm" or "rr" ? multiclass fma4s< > ... def mr : FMA4<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2, RC:$src3), !strconcat(OpcodeStr, "\t{$src3, $src2, $src1, $dst|$dst,...

On 4 August 2016 at 13:18, D'Arcy J.M. Cain <darcy at vex.net> wrote: > > Let's get this straight. You call yourself from any phone in the world > and press '*' while listening to the message, you wind up in your own > mailbox and you believe that means that you don't need a password? Do > you think that the phone syst...

...that called? Can I create a variable in the extension that I can read instead of ${CALLERID(num)}? I tried setting a random string (xaccount) and reading it with ${ENV(xaccount)} but it's not an environment variable and didn't work. Cheers. -- D'Arcy J.M. Cain System Administrator, Vex.Net http://www.Vex.Net/ IM:darcy at Vex.Net VoIP: sip:darcy at Vex.Net

...;HasVectorUAMem", "true", "Allow unaligned memory operands on vector/SIMD instructions">; should be switched-ON on AVX and AVX-512 instructions because: According to the AVX spec: "Most arithmetic and data processing instructions encoded using the VEX prefix and performing memory accesses have more flexible memory alignment requirements than instructions that are encoded without the VEX prefix. Specifically, * With the exception of explicitly aligned 16 or 32 byte SIMD load/store instructions, most VEX-encoded, arithmetic and data processing ins...