search for: verifyinstruction

Could we expose predicates defined in the target InstrInfo.td file to the MachineVerifier? We use BuildMI() to create many instructions after ISEL, but the predicates are not being checked at this point. Thus, I could forget to check the target and build an instruction that is illegal for a specific configuration. In such a case it would be nice if the MachineVerifier could detect this for me.

Matt, so in AMDGPU, the operands are sort of 'generic'? Can you point me to the right places? Thanks. On Wed, Apr 12, 2017 at 1:36 PM, Matt Arsenault <Matthew.Arsenault at amd.com> wrote: > On 04/12/2017 10:25 AM, Ryan Taylor via llvm-dev wrote: > > For example, given a multiclass for ADD 32 bit that might produce > something like: > > ADD32_REG_REG_REG