Displaying 3 results from an estimated 3 matches for "vectorunit".
2010 Jun 29
1
[PATCH]: PPC/Altivec implementations of SAD and SSD
...y ~3%,
timewise. Time spent in oc_enc_frag_sad is reduced from 4.2% to 2.3% and
oc_enc_frag_ssd from 1.2% to 1.0%, as reported by Shark.
Currently this is only integrated into the Xcode build project and need
support for detecting Altivec on platforms other than OS X; on OS X it uses
the sysctl hw.vectorunit.
Thanks,
-- vs
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://lists.xiph.org/pipermail/theora-dev/attachments/20100629/f0f421d9/attachment-0001.htm
-------------- next part --------------
A non-text attachment was scrubbed...
Name: ppcenc-draft-0.diff
Type:...
2012 Oct 05
0
[LLVMdev] LLVM Loop Vectorizer
...l have to invent an encoding and write a parser for it.
Yuck.
The upside is that it preserves the IR / codegen distinction that we've
all grown to love, and does it using a mechanism that is in LLVM terms
as old as the hills. No reviewer could argue that.
I was imagining a new "target vectorunit = "..."" string in the modules.
If you want a different way of doing it for the vector information, I
might ask that you change how TargetData works too. :)
Nick
2012 Oct 05
6
[LLVMdev] LLVM Loop Vectorizer
On Oct 5, 2012, at 12:08 AM, Nick Lewycky <nicholas at mxc.ca> wrote:
> I absolutely think that we should have something like TargetData (now DataLayout) but for the vector types and operations. However, I'm not familiar with "Target Lowering Interface". Could you explain?
I agree. Once we make the codegen accessible to the IR-level passes we need to start talking about