Displaying 11 results from an estimated 11 matches for "vectorizememoryinstruction".
2016 Aug 21
2
LoopVectorize module - some possible enhancements
...uture LLVM IR gather and scatter intrinsics
(as described at http://llvm.org/docs/LangRef.html#llvm-masked-gather-intrinsics and scatter)?
I see you have defined some methods that should use them like:
- bool isLegalMaskedGather(Type *DataType);
- void InnerLoopVectorizer::vectorizeMemoryInstruction(Instruction *Instr) which
defines a bool CreateGatherScatter, etc
I gave to clang a simple vector add C program with step/stride 2 with flag "-avx2",
but the resulting vector code does NOT use gather nor scatter.
- did you try to consider pathological cases of loops such as...
2013 Nov 15
4
[LLVMdev] Limit loop vectorizer to SSE
Something like:
index 6db7f68..68564cb 100644
--- a/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -1208,6 +1208,8 @@ void InnerLoopVectorizer::vectorizeMemoryInstruction(Instr
Type *DataTy = VectorType::get(ScalarDataTy, VF);
Value *Ptr = LI ? LI->getPointerOperand() : SI->getPointerOperand();
unsigned Alignment = LI ? LI->getAlignment() : SI->getAlignment();
+ if (Alignment == 0)
+ Alignment = 1;
unsigned AddressSpace = Ptr->getType(...
2018 Apr 11
2
Loop vectorizer doesn't try to align vectors on preferred vector alignment
...ytes. This does not correspond to the
preferred alignment for vectors that I specified in the data layout (which
is bigger).
Inspecting lib/Transforms/Vectorize/LoopVectorizer.cpp, there doesn't seem
to be an intent of doing so.
I looked at this method in particular:
void InnerLoopVectorizer::vectorizeMemoryInstruction
Is there a way (that I missed) to make this happen, or would it require a
code change ? Or did I miss anything obvious ?
Thanks in advance,
- Benoit
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2016 Sep 25
5
RFC: New intrinsics masked.expandload and masked.compressstore
...diom recognition for these
|kinds of things, and then, via that interface, let the vectorizer produce
|the relevant target-dependent intrinsics?
Entering target specific plug-in in vectorizer may be a good idea. We need target specific pattern recognition and target specific implementation of “vectorizeMemoryInstruction”. (It may be more functionality in the future)
TTI->checkAdditionalVectorizationOppotunities() - detects target specific patterns; X86 will find compress/expand and may be others
TTI->vectorizeMemoryInstruction() - handle only exotic target-specific cases
Pros:
It will allow us to implement...
2013 Nov 15
0
[LLVMdev] Limit loop vectorizer to SSE
...PM
> Subject: Re: [LLVMdev] Limit loop vectorizer to SSE
>
>
> Something like:
>
> index 6db7f68..68564cb 100644
> --- a/lib/Transforms/Vectorize/LoopVectorize.cpp
> +++ b/lib/Transforms/Vectorize/LoopVectorize.cpp
> @@ -1208,6 +1208,8 @@ void
> InnerLoopVectorizer::vectorizeMemoryInstruction(Instr
> Type *DataTy = VectorType::get(ScalarDataTy, VF);
> Value *Ptr = LI ? LI->getPointerOperand() :
> SI->getPointerOperand();
> unsigned Alignment = LI ? LI->getAlignment() : SI->getAlignment();
> + if (Alignment == 0)
> + Alignment = 1;
That may...
2013 Nov 15
2
[LLVMdev] Limit loop vectorizer to SSE
...loop vectorizer to SSE
>>
>>
>> Something like:
>>
>> index 6db7f68..68564cb 100644
>> --- a/lib/Transforms/Vectorize/LoopVectorize.cpp
>> +++ b/lib/Transforms/Vectorize/LoopVectorize.cpp
>> @@ -1208,6 +1208,8 @@ void
>> InnerLoopVectorizer::vectorizeMemoryInstruction(Instr
>> Type *DataTy = VectorType::get(ScalarDataTy, VF);
>> Value *Ptr = LI ? LI->getPointerOperand() :
>> SI->getPointerOperand();
>> unsigned Alignment = LI ? LI->getAlignment() : SI->getAlignment();
>> + if (Alignment == 0)
>> + Align...
2016 Sep 19
2
RFC: New intrinsics masked.expandload and masked.compressstore
Hi all,
AVX-512 ISA introduces new vector instructions VCOMPRESS and VEXPAND in order to allow vectorization of the following loops with two specific types of cross-iteration dependencies:
Compress:
for (int i=0; i<N; ++i)
If (t[i])
*A++ = expr;
Expand:
for (i=0; i<N; ++i)
If (t[i])
X[i] = *A++;
else
2016 Sep 26
2
RFC: New intrinsics masked.expandload and masked.compressstore
...e special patterns that will require a separate analysis. I thought about other X86 specific patterns that may be detected. Strided memory access with masks or arithmetic with saturation. But again, I'm not sure that constructing plug-in will not be an overkill in this case.
|
|> TTI->vectorizeMemoryInstruction() - handle only exotic
|> target-specific cases
|>
|> Pros:
|> It will allow us to implement all X86 specific solutions.
|> The expandload and compresssrore intrinsics may be x86 specific,
|> polymorphic:
|> llvm.x86.masked.expandload()
|> llvm.x86.masked.co...
2018 Apr 12
0
Loop vectorizer doesn't try to align vectors on preferred vector alignment
...a layout (which
>> is bigger).
>>
>>
>>
>> Inspecting lib/Transforms/Vectorize/LoopVectorizer.cpp, there doesn't
>> seem to be an intent of doing so.
>>
>> I looked at this method in particular:
>>
>>
>> void InnerLoopVectorizer::vectorizeMemoryInstruction
>>
>>
>>
>> Is there a way (that I missed) to make this happen, or would it require a
>> code change ? Or did I miss anything obvious ?
>>
>>
>>
>>
>>
>> If the original pointer before vectorization is aligned on 2 bytes
>> bou...
2013 Nov 15
0
[LLVMdev] Limit loop vectorizer to SSE
Nadav,
I believe aligned accesses to unaligned pointers is precisely the issue.
Consider the function `add_u8S` before[1] and after[2] the loop vectorizer
pass. There is no alignment assumption associated with %kernel_data prior
to vectorization. I can't tell if it's the loop vectorizer or the codegen
at fault, but the alignment assumption seems to sneak in somewhere.
v/r,
Josh
[1]
2013 Nov 15
6
[LLVMdev] Limit loop vectorizer to SSE
On Nov 15, 2013, at 12:36 PM, Renato Golin <renato.golin at linaro.org> wrote:
> On 15 November 2013 20:24, Joshua Klontz <josh.klontz at gmail.com> wrote:
> Agreed, is there a pass that will insert a runtime alignment check? Also, what's the easiest way to get at TargetTransformInfo::getRegisterBitWidth() so I don't have to hard code 32? Thanks!
>
> I think