Displaying 7 results from an estimated 7 matches for "vectoraddr".
Did you mean:
vectoradd
2010 May 05
1
[LLVMdev] Size of packed struct type <{<3 x i32>, i32}>
...p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-pc-linux"
%mytype = type <{<3 x i32>, i32}>
define void @myexample(%mytype* %src, i64 %index, i32* %result) {
entry:
%vectoraddr = getelementptr %mytype* %src, i64 %index, i32 0
%vector = load <3 x i32>* %vectoraddr
%tmp1 = extractelement <3 x i32> %vector, i32 2
store i32 %tmp1, i32* %result
ret void
}
When I generate code (llc revision: 103084) i get:
.Leh_func_begin0:
# BB#0:...
2016 Dec 15
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...ass X86VMemOperand<RegisterClass RC, string printMethod>
> : X86MemOperand<printMethod> {
> let MIOperandInfo = (ops i8imm, RC, i32imm);
> }
> def vx256xmem : X86VMemOperand<MSA128D, "printi256mem">;
>
> def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>;
>
> class LD_INDIRECT_DESC_BASE2<string instr_asm,
> RegisterOperand ROWD,
> RegisterOperand ROWSP = ROWD,
>...
2016 Dec 12
0
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...mem operands
class X86VMemOperand<RegisterClass RC, string printMethod>
: X86MemOperand<printMethod> {
let MIOperandInfo = (ops i8imm, RC, i32imm);
}
def vx256xmem : X86VMemOperand<MSA128D, "printi256mem">;
def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>;
class LD_INDIRECT_DESC_BASE2<string instr_asm,
RegisterOperand ROWD,
RegisterOperand ROWSP = ROWD,...
2016 Dec 11
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
Hello.
Will, thanks a lot for pointing me to the MaskedGatherSDNode and mgatherv4i32. I have
to say that the definition of the "multiclass avx512_gather" from
lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use it.
I currently have some serious problems with TableGen - it gives an assertion failure:
2017 Aug 07
2
VBROADCAST Implementation Issues
...CWM:$mask, memop:$src2),
> !strconcat(OpcodeStr#_.Suffix,
> "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
> [(set _.RC:$dst, _.KRCWM:$mask_wb,
> (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
> vectoraddr:$src2))]>, EVEX, EVEX_K,
> EVEX_CD8<_.EltSize, CD8VT1>;
> }
>
> ~Craig
>
> On Sun, Aug 6, 2017 at 2:21 PM, hameeza ahmed <hahmed2305 at gmail.com>
> wrote:
>
>> i want to implement gather for v64i32. i wrote following code.
>>
>>...
2017 Aug 07
3
VBROADCAST Implementation Issues
....Suffix,
>>>>> "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
>>>>> [(set _.RC:$dst, _.KRCWM:$mask_wb,
>>>>> (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
>>>>> vectoraddr:$src2))]>, EVEX, EVEX_K,
>>>>> EVEX_CD8<_.EltSize, CD8VT1>;
>>>>> }
>>>>>
>>>>> ~Craig
>>>>>
>>>>> On Sun, Aug 6, 2017 at 2:21 PM, hameeza ahmed <hahmed2305 at gmail.com>
>>&g...
2017 Aug 06
2
VBROADCAST Implementation Issues
i want to implement gather for v64i32. i wrote following code.
def GATHER_256B : I<0x68, MRMSrcMem, (outs VR_2048:$dst), (ins
i2048mem:$src),
"GATHER_256B\t{$src, $dst|$dst, $src}",
[(set VR_2048:$dst, (v64i32 (masked_gather
addr:$src)))],
IIC_MOV_MEM>, TA;
def: Pat<(v64f32 (masked_gather addr:$src)), (GATHER_256B