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Dear all, I have just created a couple of differential reviews to enable the vectorisation of loops that have function calls to routines marked with “#pragma omp declare simd”. They can be (re)viewed here: * https://reviews.llvm.org/D27249 * https://reviews.llvm.org/D27250 The current implementation allows the loop vectorizer to generate vector code for source file as: #pragma omp declare

...ides. This is not the same on Intel, for example when this code generates vector names for AVX and AVX2. The register width for these architecture extensions are the same, so all the TLI has is a mapping between scalar name and (vectro_name, function_type) who's two elements differ only in the vector_name string. This breaks the target independence of the vectorizer, as it would require it to parse the vector_name to be able to choose between the AVX or the AVX2 implementation. Now, to make this work one should have to encode the SSE/SSE2/AVX/AVX2 information in the VectorFnInfo structure. Does an...

...ot the same on Intel, for example when this code generates >vector names for AVX and AVX2. The register width for these architecture >extensions are the same, so all the TLI has is a mapping between scalar >name and (vectro_name, function_type) who's two elements differ only in >the vector_name string. > >This breaks the target independence of the vectorizer, as it would >require it to parse the vector_name to be able to choose between the AVX >or the AVX2 implementation. > >Now, to make this work one should have to encode the SSE/SSE2/AVX/AVX2 >information in the Vec...