Displaying 2 results from an estimated 2 matches for "vector_add_float".
2011 Sep 27
2
[LLVMdev] Poor code generation for odd sized vectors
Hi all,
I'm compiling LLCM IR code like this on x86-64:
define linkonce ccc <16 x float> @vector_add_float(<16 x float> %a.78, <16 x float> %a.79) align 8
{
entry:
%result.80 = fadd <16 x float> %a.78, %a.79
ret <18 x float> %result.80
}
This works really well when the vector length (16 in the above) is
an integer multiple of the SSE vector register width (4) r...
2011 Sep 27
0
[LLVMdev] Poor code generation for odd sized vectors
...please open a bugreport. The LLVM type legalizer has a
bunch of code to handle this (vector widening), but unfortunately the argument
lowering code seems to have scalarized the function arguments before getting
to the type legalizer. Compare with the code produced for the following:
define void @vector_add_float(<18 x float> *%rp, <18 x float> *%a.78p, <18 x
float> *%a.79p) {
%a.78 = load <18 x float> *%a.78p
%a.79 = load <18 x float> *%a.79p
%result.80 = fadd <18 x float> %a.78, %a.79
store <18 x float> %result.80, <18 x float> *%rp
ret voi...