Displaying 6 results from an estimated 6 matches for "vecload".
2016 Mar 10
2
masked-load endpoints optimization
...= call <4 x i32> @llvm.masked.load.v4i32(<4 x i32>* %addr, i32 4, <4
x i1> <i1 1, i1 0, i1 0, i1 1>, <4 x i32> %v)
ret <4 x i32> %res
}
would become something like:
define <4 x i32> @maskedload_endpoints(<4 x i32>* %addr, <4 x i32> %v) {
%vecload = load <4 x i32>, <4 x i32>* %addr, align 4
%sel = select <4 x i1> <i1 1, i1 0, i1 0, i1 1>, <4 x i32> %vecload, <4 x
i32> %v
ret <4 x i32> %sel
}
If this isn't valid as an IR optimization, would it be acceptable as a DAG
combine with target hook t...
2016 Mar 11
3
masked-load endpoints optimization
...<4 x i32>* %addr, i32 4,
> <4 x i1> <i1 1, i1 0, i1 0, i1 1>, <4 x i32> %v)
> ret <4 x i32> %res
> }
>
> would become something like:
>
>
> define <4 x i32> @maskedload_endpoints(<4 x i32>* %addr, <4 x i32> %v) {
>
> %vecload = load <4 x i32>, <4 x i32>* %addr, align 4
>
> %sel = select <4 x i1> <i1 1, i1 0, i1 0, i1 1>, <4 x i32> %vecload, <4
> x i32> %v
>
> ret <4 x i32> %sel
> }
>
> If this isn't valid as an IR optimization, would it be accepta...
2016 Mar 15
3
the as-if rule / perf vs. security
...<4 x i32>* %addr, i32 4,
> <4 x i1> <i1 1, i1 0, i1 0, i1 1>, <4 x i32> %v)
> ret <4 x i32> %res
> }
>
> would become something like:
>
>
> define <4 x i32> @maskedload_endpoints(<4 x i32>* %addr, <4 x i32> %v) {
>
> %vecload = load <4 x i32>, <4 x i32>* %addr, align 4
>
> %sel = select <4 x i1> <i1 1, i1 0, i1 0, i1 1>, <4 x i32> %vecload, <4
> x i32> %v
>
> ret <4 x i32> %sel
> }
>
> If this isn't valid as an IR optimization, would it be accepta...
2016 Mar 16
3
the as-if rule / perf vs. security
...<4 x i1> <i1 1, i1 0, i1 0, i1 1>, <4 x i32> %v)
>> ret <4 x i32> %res
>> }
>>
>> would become something like:
>>
>>
>> define <4 x i32> @maskedload_endpoints(<4 x i32>* %addr, <4 x i32> %v) {
>>
>> %vecload = load <4 x i32>, <4 x i32>* %addr, align 4
>>
>> %sel = select <4 x i1> <i1 1, i1 0, i1 0, i1 1>, <4 x i32> %vecload, <4
>> x i32> %v
>>
>> ret <4 x i32> %sel
>> }
>>
>> If this isn't valid as an IR o...
2016 Mar 16
3
the as-if rule / perf vs. security
...i1 1>, <4 x i32> %v)
>>> ret <4 x i32> %res
>>> }
>>>
>>> would become something like:
>>>
>>>
>>> define <4 x i32> @maskedload_endpoints(<4 x i32>* %addr, <4 x i32> %v) {
>>>
>>> %vecload = load <4 x i32>, <4 x i32>* %addr, align 4
>>>
>>> %sel = select <4 x i1> <i1 1, i1 0, i1 0, i1 1>, <4 x i32> %vecload,
>>> <4 x i32> %v
>>>
>>> ret <4 x i32> %sel
>>> }
>>>
>>> If...
2006 Apr 13
3
[LLVMdev] Re: Creating Release 1.7 Branch at 1:00pm PDT
Here's what's left on Linux (GCC 4.1.0), after all updates that went
into the branch:
Running /proj/llvm/build/../llvm/test/Regression/CFrontend/dg.exp ...
FAIL: /proj/llvm/build/../llvm/test/Regression/CFrontend/2004-02-12-
LargeAggregateCopy.c.tr:
gccas: /proj/llvm/build/../llvm/lib/VMCore/Function.cpp:266: unsigned
int llvm::Function::getIntrinsicID() const: Assertion `0 &&