Displaying 4 results from an estimated 4 matches for "vecext5".
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vecext4
2017 Sep 14
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...; preds = %entry,
%for.cond
%i.022 = phi i32 [ 0, %entry ], [ %inc, %for.cond ]
%0 = icmp ne <2 x i32> %vecinit1, <i32 0, i32 -23>
%1 = extractelement <2 x i1> %0, i32 %i.022
%vecext4 = extractelement <2 x i32> %vecinit1, i32 %i.022
%vecext5 = extractelement <2 x i32> <i32 0, i32 -23>, i32 %i.022
%cmp6 = icmp ne i32 %vecext4, %vecext5
%cmp7 = xor i1 %1, %cmp6
...
and the SelectionDAG before TypeLegalizer is like this.
t0: ch = EntryToken
t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0
t3: ch = ValueType:i...
2017 Sep 15
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...; preds = %entry,
> %for.cond
> %i.022 = phi i32 [ 0, %entry ], [ %inc, %for.cond ]
> %0 = icmp ne <2 x i32> %vecinit1, <i32 0, i32 -23>
> %1 = extractelement <2 x i1> %0, i32 %i.022
> %vecext4 = extractelement <2 x i32> %vecinit1, i32 %i.022
> %vecext5 = extractelement <2 x i32> <i32 0, i32 -23>, i32 %i.022
> %cmp6 = icmp ne i32 %vecext4, %vecext5
> %cmp7 = xor i1 %1, %cmp6
>
> ...
>
> and the SelectionDAG before TypeLegalizer is like this.
>
> t0: ch = EntryToken
> t2: i32,ch = CopyFromReg t0, Regis...
2017 Sep 17
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...; preds = %entry,
%for.cond
%i.022 = phi i32 [ 0, %entry ], [ %inc, %for.cond ]
%0 = icmp ne <2 x i32> %vecinit1, <i32 0, i32 -23>
%1 = extractelement <2 x i1> %0, i32 %i.022
%vecext4 = extractelement <2 x i32> %vecinit1, i32 %i.022
%vecext5 = extractelement <2 x i32> <i32 0, i32 -23>, i32 %i.022
%cmp6 = icmp ne i32 %vecext4, %vecext5
%cmp7 = xor i1 %1, %cmp6
...
and the SelectionDAG before TypeLegalizer is like this.
t0: ch = EntryToken
t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0
t3: ch = ValueT...
2017 Sep 18
1
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...; preds = %entry,
%for.cond
%i.022 = phi i32 [ 0, %entry ], [ %inc, %for.cond ]
%0 = icmp ne <2 x i32> %vecinit1, <i32 0, i32 -23>
%1 = extractelement <2 x i1> %0, i32 %i.022
%vecext4 = extractelement <2 x i32> %vecinit1, i32 %i.022
%vecext5 = extractelement <2 x i32> <i32 0, i32 -23>, i32 %i.022
%cmp6 = icmp ne i32 %vecext4, %vecext5
%cmp7 = xor i1 %1, %cmp6
...
and the SelectionDAG before TypeLegalizer is like this.
t0: ch = EntryToken
t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0
t3: ch = ValueT...