Displaying 4 results from an estimated 4 matches for "vec30".
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vec3
2016 Jun 15
3
[Proposal][RFC] Strided Memory Access Vectorization
...0, i32 undef, i32 undef, i32 1>
call void @llvm.masked.store.v4i32(<4 x i32> %interleaved.vec, <4 x i32>* %11, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 true>)
%12 = getelementptr i32, i32* %10, i64 6
%13 = bitcast i32* %12 to <4 x i32>*
%interleaved.vec30 = shufflevector <4 x i32> %StoreResult, <4 x i32> undef, <4 x i32> <i32 2, i32 undef, i32 undef, i32 3>
call void @llvm.masked.store.v4i32(<4 x i32> %interleaved.vec30, <4 x i32>* %13, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 true>)
NOTE: F...
2016 Jun 18
2
[Proposal][RFC] Strided Memory Access Vectorization
...i32 1>
> call void @llvm.masked.store.v4i32(<4 x i32> %interleaved.vec, <4 x
> i32>* %11, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 true>)
> %12 = getelementptr i32, i32* %10, i64 6
> %13 = bitcast i32* %12 to <4 x i32>*
> %interleaved.vec30 = shufflevector <4 x i32> %StoreResult, <4 x i32>
> undef,
> <4 x i32> <i32 2, i32 undef, i32 undef, i32 3>
> call void @llvm.masked.store.v4i32(<4 x i32> %interleaved.vec30, <4
> x i32>* %13, i32 4, <4 x i1> <i1 true, i1 false, i1 false,...
2016 Jun 30
0
[Proposal][RFC] Strided Memory Access Vectorization
...ll void @llvm.masked.store.v4i32(<4 x i32> %interleaved.vec, <4 x
> > i32>* %11, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 true>)
> > %12 = getelementptr i32, i32* %10, i64 6
> > %13 = bitcast i32* %12 to <4 x i32>*
> > %interleaved.vec30 = shufflevector <4 x i32> %StoreResult, <4 x i32>
> > undef,
> > <4 x i32> <i32 2, i32 undef, i32 undef, i32 3>
> > call void @llvm.masked.store.v4i32(<4 x i32> %interleaved.vec30, <4
> > x i32>* %13, i32 4, <4 x i1> <i1 true, i...
2016 Jun 30
1
[Proposal][RFC] Strided Memory Access Vectorization
...vm.masked.store.v4i32(<4 x i32> %interleaved.vec, <4
> > x
> > i32>* %11, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 true>)
> > %12 = getelementptr i32, i32* %10, i64 6
> > %13 = bitcast i32* %12 to <4 x i32>*
> > %interleaved.vec30 = shufflevector <4 x i32> %StoreResult, <4 x
> > i32> undef,
> > <4 x i32> <i32 2, i32 undef, i32 undef, i32 3>
> > call void @llvm.masked.store.v4i32(<4 x i32> %interleaved.vec30,
> > <4 x i32>* %13, i32 4, <4 x i1> <i1 true,...