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--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68 On Thu, Jan 31, 2019 at 10:22 PM Jacob Lifshay <programmerjake at gmail.com> wrote: > > We're in-progress designing a RISC-V extension (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-January/000433.html) that would have variable-length vectors of short vectors (1 to 4): > <VL x <4 x

...better to be able to have a > > single bit of a predicate apply to the *entire* vec3 or vec4 type, on > > each outer loop. > > This situation can be handled easily in the standard RISC-V vector > extension. You'd do something like... > > vsetvli t0, a0, vsew128,vnreg8,vdiv4 > > ... to configure the vector unit to provide eight vector register > variables divided into a standard element width of 128 bits (some > instructions will widen or narrow one step to/from 64 bits or 256 > bits), and then dividing each 128 bit element into 4 parts. > > Arithm...