search for: vdd_core

...s can also contain > a voltage to be applied to the volt device (not yet implemented in this > series). > Yes. For Tegra I think it makes sense to move DVS out of the individual drivers. Then we can share the code which has to deal with building the OPP tables with other DVS rails (eg. vdd_core) for example. Often there are also chip specific quirks to be dealt with (such as the maximum allowed voltage step or voltage relationships between rails), which are easier to handle in common code. Cheers, Peter.

On 07/10/2014 06:43 PM, Peter De Schrijver wrote: > On Thu, Jul 10, 2014 at 09:34:34AM +0200, Alexandre Courbot wrote: >> This series adds support for reclocking on GK20A. The first two patches touch >> the clock subsystem to allow GK20A to operate, by making the presence of the >> thermal and voltage devices optional, and allowing pstates to be provided >> directly