search for: vcvtps2ph

Displaying 5 results from an estimated 5 matches for "vcvtps2ph".

2015 Sep 08
2
Strange types on x86 vcvtph2ps and vcvtps2ph intrinsics
...quot;__builtin_ia32_vcvtph2ps">, Intrinsic<[llvm_v4f32_ty], [llvm_v8i16_ty], [IntrNoMem]>; def int_x86_vcvtph2ps_256 : GCCBuiltin<"__builtin_ia32_vcvtph2ps256">, Intrinsic<[llvm_v8f32_ty], [llvm_v8i16_ty], [IntrNoMem]>; def int_x86_vcvtps2ph_128 : GCCBuiltin<"__builtin_ia32_vcvtps2ph">, Intrinsic<[llvm_v8i16_ty], [llvm_v4f32_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_vcvtps2ph_256 : GCCBuiltin<"__builtin_ia32_vcvtps2ph256">, Intrinsic<[llvm_...
2019 Jan 22
4
_Float16 support
...I suppose, except for the fact that it hasn't taken the lack of target support for half-precision arithmetic into account yet. That will happen in the selection DAG. The assembly code generated looks like this (with my annotations): f: # @f # %bb.0: vcvtps2ph xmm1, xmm1, 4 # Convert argument 1 from single to half vcvtph2ps xmm1, xmm1 # Convert argument 1 back to single vcvtps2ph xmm0, xmm0, 4 # Convert argument 0 from single to half vcvtph2ps xmm0, xmm0...
2019 Jan 24
2
[cfe-dev] _Float16 support
...ept for the fact that it hasn’t taken the lack of target support for half-precision arithmetic into account yet. That will happen in the selection DAG. The assembly code generated looks like this (with my annotations): > > f: # @f > # %bb.0: > vcvtps2ph xmm1, xmm1, 4 # Convert argument 1 from single to half > vcvtph2ps xmm1, xmm1 # Convert argument 1 back to single > vcvtps2ph xmm0, xmm0, 4 # Convert argument 0 from single to half > vcvtph2ps xmm0, xmm0...
2019 Jan 24
4
[cfe-dev] _Float16 support
...n the lack of target support for half-precision >> arithmetic into account yet. That will happen in the selection DAG. >> The assembly code generated looks like this (with my annotations): >> >> f: # @f >> # %bb.0: >> vcvtps2ph xmm1, xmm1, 4 # Convert argument 1 >> from single to half >> vcvtph2ps xmm1, xmm1 # Convert argument >> 1 back to single >> vcvtps2ph xmm0, xmm0, 4 # Convert argument 0 >> from single to half &g...
2014 Jun 19
2
[LLVMdev] __fp16 suport in llvm back-end
Hi, all: I am trying to test half float point support in llvm, I found clang can generate bitcode for __fp16, while llc can't generate code for it, the error message is like this LLVM ERROR: Cannot select: 0x26a68e0: i16 = fp32_to_fp16 0x26a67d8 [ORD=2] [ID=4] 0x26a67d8: f32,ch = CopyFromReg 0x2693060, 0x26a66d0 [ORD=2] [ID=3] 0x26a66d0: f32 = Register %vreg1 [ID=1] In function: test