search for: vco

For some reason max_vco was set to a lower value that it can support, which prevented some clock states to be applied. Fix this by setting it to the same value as downstream. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- nvkm/subdev/clock/gk20a.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-...

...ng my Linux-box joined our AD Windows 2000 Server? I'm using Fedora Core 1, I've installed samba and krb5-workstation and SWAT. I configured samba, but I would like to check it with some of you! In fact, I get following errors when trying to join: [root@boniforti root]# net ads join DOM-VCO -U Administrator Administrator password: [2004/02/26 14:08:37, 0] libads/kerberos.c:ads_kinit_password(133) kerberos_kinit_password Administrator@PROVINCIA.VERBANIA.IT failed: Cannot find KDC for requested realm [root@boniforti root]# kinit administrator@provincia.verbania.it kinit(v5): Cannot...

Okay...here's one for all of you.... 3 party meet-me conference: Call 1: Comes in to MyAsterisk on an E1 PRI into the system. All TDM, no VoIP at all involved. No echo at all. Call 2: Call comes in via IAX....(TDM -> Asterisk_1 -> IAX/GSM -> MyAsterisk. Caller immediately hears his own echo Call 3: Call comes in via IAX....(TDM -> Asterisk_1 -> IAX/GSM -> MyAsterisk.

...ese in for 4.6. Not too big a deal if you cannot however. Alexandre Courbot (15): volt/gk20a: split constructor volt: add GM20B driver clk/gk20a: convert parameters to Khz clk/gk20a: reorganize variables in gk20a_pllg_calc_mnp() clk/gk20a: rename enable/disable functions clk/gk20a: fix VCO bit mask clk/gk20a: only compute n_lo if needed clk/gk20a: only restore divider to 1:1 if needed clk/gk20a: emit parent rate as debug message clk/gk20a: put mnp values into their own struct clk/gk20a: abstract pl_to_div clk/gk20a: split gk20a_clk_new() clk/gk20a: set lowest frequency...

...SYS_GPCPLL_CFG_BASE + 0x1c) +#define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 0 +#define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8 +#define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 16 +#define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 22 +#define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 31 + +#define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100) +#define SEL_VCO_GPC2CLK_OUT_SHIFT 0 + +#define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250) +#define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1 +#define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31 +#define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define GPC2CLK_OUT_VCODIV_WIDTH 6 +#define...

This series adds support for GM20B PLL's Maxwell features, namely glitchless switch and (more importantly) DFS support. DFS lets the PLL lower its output speed according to input current variations, making the clock more stable and allowing it to run safely at lower voltage. All GM20B additions are done in the last patch, which consequently ends up being considerably big ; fortunately, it

...define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 0 > +#define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8 > +#define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 16 > +#define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 22 > +#define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 31 > + > +#define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100) > +#define SEL_VCO_GPC2CLK_OUT_SHIFT 0 > + > +#define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250) > +#define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1 > +#define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31 > +#define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 > +#define G...

This series adds support for reclocking on GK20A. The first two patches touch the clock subsystem to allow GK20A to operate, by making the presence of the thermal and voltage devices optional, and allowing pstates to be provided directly instead of being probed using the BIOS (which Tegra does not have). The last patch adds the GK20A clock device. Arguably the clock can be seen as a stripped-down

Second version of the gk20a clock patches. I have tried to keep the therm and volt devices mandatory in the clock driver, but unfortunately they are too tied to bios to allow this, at least for the moment. Consequently this version is mostly a port of the first version to Ben's tree. Ben, please let me know what I have done wrong in terms of integration to your tree, as the main purpose of

...rom_pstate(u32 pstate) -{ - u32 hi, lo; - rdmsr(MSR_PSTATE_DEF_BASE + pstate, lo, hi); - return (lo & HW_PSTATE_DID_MASK) >> HW_PSTATE_DID_SHIFT; +static u32 find_khz_freq_from_pstate(struct cpufreq_frequency_table *data, u32 pstate) +{ + return data[pstate].frequency; } /* Return the vco fid for an input fid @@ -139,9 +118,7 @@ static int query_current_values_with_pen if (cpu_family == CPU_HW_PSTATE) { rdmsr(MSR_PSTATE_STATUS, lo, hi); i = lo & HW_PSTATE_MASK; - rdmsr(MSR_PSTATE_DEF_BASE + i, lo, hi); - data->currfid = lo & HW_PSTATE_FID_MASK; - data->currd...

https://bugs.freedesktop.org/show_bug.cgi?id=97620 Bug ID: 97620 Summary: [REGRESSION] KMS having issues after kernel upgrade (4.5.1-1 to 4.6.4-1) Product: xorg Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: critical Priority: medium

...et_cntls R128: don't clip modes to panel on laptops when only using the CRT port RADEON: fix palette when depth != 24 RADEON: fix randr on r4xx RADEON: hack around console restore hang on r4xx RADEON: write out saved vclk and pixclk values RADEON: Compute PLL VCO gain RADEON: Initial pass at integrated tv out support RADEON: add info about tv out code and authorship RADEON: tv-out fixes. works now. tested on rv350. RADEON: fix name of tv output RADEON: more fixes... RADEON: convert hard coded tv out values to calculatio...

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depends on "autoconf: regenerate configure scripts with 4.4 version" This series removes some of the really old deadwood from the tools build and makes some other things which are on their way out configurable at build time with a default depending on how far down the slope I judge them to be. * nuke in tree copy of libaio * nuke obsolete tools: xsview, miniterm, lomount & sv *