search for: vc_insn_string_read

On Tue, Apr 28, 2020 at 05:16:33PM +0200, Joerg Roedel wrote: > @@ -63,3 +175,45 @@ void __init do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code) > while (true) > asm volatile("hlt\n"); > } > + > +static enum es_result vc_insn_string_read(struct es_em_ctxt *ctxt, > + void *src, char *buf, > + unsigned int data_size, > + unsigned int count, > + bool backwards) > +{ > + int i, b = backwards ? -1 : 1; > + enum es_result ret = ES_OK; > + > + for (i = 0; i < count; i++) { > + void...

...ount = (exit_info_1 & IOIO_REP) ? regs->cx : 1; > + exit_info_2 = min(op_count, ghcb_count); > + exit_bytes = exit_info_2 * io_bytes; > + > + es_base = insn_get_seg_base(ctxt->regs, INAT_SEG_REG_ES); > + > + if (!(exit_info_1 & IOIO_TYPE_IN)) { > + ret = vc_insn_string_read(ctxt, > + (void *)(es_base + regs->si), SEV(-ES) is 64-bit only, why bother with the es_base charade? > + ghcb->shared_buffer, io_bytes, > + exit_info_2, df); df handling is busted, it's aways non-zero. Same goes for the SI/DI adjustments belo...

...ount = (exit_info_1 & IOIO_REP) ? regs->cx : 1; > + exit_info_2 = min(op_count, ghcb_count); > + exit_bytes = exit_info_2 * io_bytes; > + > + es_base = insn_get_seg_base(ctxt->regs, INAT_SEG_REG_ES); > + > + if (!(exit_info_1 & IOIO_TYPE_IN)) { > + ret = vc_insn_string_read(ctxt, > + (void *)(es_base + regs->si), SEV(-ES) is 64-bit only, why bother with the es_base charade? > + ghcb->shared_buffer, io_bytes, > + exit_info_2, df); df handling is busted, it's aways non-zero. Same goes for the SI/DI adjustments belo...

...ust a reminder so that this doesn't get lost: On Tue, Apr 28, 2020 at 05:16:35PM +0200, Joerg Roedel wrote: > + if (exit_info_1 & IOIO_TYPE_STR) { > + int df = (regs->flags & X86_EFLAGS_DF) ? -1 : 1; ... > + > + if (!(exit_info_1 & IOIO_TYPE_IN)) { > + ret = vc_insn_string_read(ctxt, > + (void *)(es_base + regs->si), > + ghcb->shared_buffer, io_bytes, > + exit_info_2, df); ^^^^ > + > + /* Everything went well, write back results */ > + if (exit_info_1 & IOIO_TYPE_IN) { > + ret = vc_insn_string_...

...EP) ? regs->cx : 1; > > + exit_info_2 = min(op_count, ghcb_count); > > + exit_bytes = exit_info_2 * io_bytes; > > + > > + es_base = insn_get_seg_base(ctxt->regs, INAT_SEG_REG_ES); > > + > > + if (!(exit_info_1 & IOIO_TYPE_IN)) { > > + ret = vc_insn_string_read(ctxt, > > + (void *)(es_base + regs->si), > > SEV(-ES) is 64-bit only, why bother with the es_base charade? User-space can also cause IOIO #VC exceptions, and user-space can be 32-bit legacy code with segments, so es_base has to be taken into account. > > > +...

...t; + exit_info_2 = min(op_count, ghcb_count); > > > + exit_bytes = exit_info_2 * io_bytes; > > > + > > > + es_base = insn_get_seg_base(ctxt->regs, INAT_SEG_REG_ES); > > > + > > > + if (!(exit_info_1 & IOIO_TYPE_IN)) { > > > + ret = vc_insn_string_read(ctxt, > > > + (void *)(es_base + regs->si), > > > > SEV(-ES) is 64-bit only, why bother with the es_base charade? > > User-space can also cause IOIO #VC exceptions, and user-space can be > 32-bit legacy code with segments, so es_base has to be taken int...

...t; + exit_info_2 = min(op_count, ghcb_count); > > > + exit_bytes = exit_info_2 * io_bytes; > > > + > > > + es_base = insn_get_seg_base(ctxt->regs, INAT_SEG_REG_ES); > > > + > > > + if (!(exit_info_1 & IOIO_TYPE_IN)) { > > > + ret = vc_insn_string_read(ctxt, > > > + (void *)(es_base + regs->si), > > > > SEV(-ES) is 64-bit only, why bother with the es_base charade? > > User-space can also cause IOIO #VC exceptions, and user-space can be > 32-bit legacy code with segments, so es_base has to be taken int...

...hared_buffer) / io_bytes; + + op_count = (exit_info_1 & IOIO_REP) ? regs->cx : 1; + exit_info_2 = min(op_count, ghcb_count); + exit_bytes = exit_info_2 * io_bytes; + + es_base = insn_get_seg_base(ctxt->regs, INAT_SEG_REG_ES); + + if (!(exit_info_1 & IOIO_TYPE_IN)) { + ret = vc_insn_string_read(ctxt, + (void *)(es_base + regs->si), + ghcb->shared_buffer, io_bytes, + exit_info_2, df); + if (ret) + return ret; + } + + sw_scratch = __pa(ghcb) + offsetof(struct ghcb, shared_buffer); + ghcb_set_sw_scratch(ghcb, sw_scratch); + ret = sev_es_ghcb_hv...

...is is the first VC handler during boot, there is no GHCB * page yet, so it only supports the MSR based communication with the @@ -63,3 +175,45 @@ void __init do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code) while (true) asm volatile("hlt\n"); } + +static enum es_result vc_insn_string_read(struct es_em_ctxt *ctxt, + void *src, char *buf, + unsigned int data_size, + unsigned int count, + bool backwards) +{ + int i, b = backwards ? -1 : 1; + enum es_result ret = ES_OK; + + for (i = 0; i < count; i++) { + void *s = src + (i * data_size * b); + char *d = buf...

Hi, here is the next version of changes to enable Linux to run as an SEV-ES guest. The code was rebased to v5.7-rc3 and got a fair number of changes since the last version. What is SEV-ES ============== SEV-ES is an acronym for 'Secure Encrypted Virtualization - Encrypted State' and means a hardware feature of AMD processors which hides the register state of VCPUs to the hypervisor by

Hi, here is the next version of changes to enable Linux to run as an SEV-ES guest. The code was rebased to v5.7-rc3 and got a fair number of changes since the last version. What is SEV-ES ============== SEV-ES is an acronym for 'Secure Encrypted Virtualization - Encrypted State' and means a hardware feature of AMD processors which hides the register state of VCPUs to the hypervisor by

From: Joerg Roedel <jroedel at suse.de> Hi, here is a rebased version of the latest SEV-ES patches. They are now based on latest tip/master instead of upstream Linux and include the necessary changes. Changes to v4 are in particular: - Moved early IDT setup code to idt.c, because the idt_descr and the idt_table are now static - This required to make stack protector work early (or

From: Joerg Roedel <jroedel at suse.de> Hi, here is the fourth version of the SEV-ES Guest Support patches. I addressed the review comments sent to me for the previous version and rebased the code v5.8-rc5. The biggest change in this version is the IST handling code for the #VC handler. I adapted the entry code for the #VC handler to the big pile of entry code changes merged into

From: Joerg Roedel <jroedel at suse.de> Hi, here is the fourth version of the SEV-ES Guest Support patches. I addressed the review comments sent to me for the previous version and rebased the code v5.8-rc5. The biggest change in this version is the IST handling code for the #VC handler. I adapted the entry code for the #VC handler to the big pile of entry code changes merged into

From: Joerg Roedel <jroedel at suse.de> Hi, here is the new version of the SEV-ES client enabling patch-set. It is based on the latest tip/master branch and contains the necessary changes. In particular those ar: - Enabling CR4.FSGSBASE early on supported processors so that early #VC exceptions on APs can be handled. - Add another patch (patch 1) to fix a KVM frame-size build

From: Joerg Roedel <jroedel at suse.de> Hi, here is a new version of the SEV-ES Guest Support patches for x86. The previous versions can be found as a linked list starting here: https://lore.kernel.org/lkml/20200824085511.7553-1-joro at 8bytes.org/ I updated the patch-set based on ther review comments I got and the discussions around it. Another important change is that the early IDT

From: Joerg Roedel <jroedel at suse.de> Hi, here is a new version of the SEV-ES Guest Support patches for x86. The previous versions can be found as a linked list starting here: https://lore.kernel.org/lkml/20200824085511.7553-1-joro at 8bytes.org/ I updated the patch-set based on ther review comments I got and the discussions around it. Another important change is that the early IDT