search for: varinfo

...++++++++++++-- include/dis.h | 3 +++ 4 files changed, 24 insertions(+), 4 deletions(-) diff --git a/envydis/core-as.c b/envydis/core-as.c index ce87653..ee9cd21 100644 --- a/envydis/core-as.c +++ b/envydis/core-as.c @@ -741,7 +741,7 @@ struct matches *do_as(const struct disisa *isa, struct varinfo *varinfo, struct struct iasctx c = { isa, varinfo }; struct iasctx *ctx = &c; convert_insn(ctx, insn); - struct matches *m = atomtab_a(ctx, isa->troot, 0); + struct matches *m = atomtab_a(ctx, isa->trootas ?: isa->troot, 0); int i; for (i = 0; i < m->mnum; i++) if (m...

...%ZERO, <BB#17>; CPURegs:%vreg81 J <BB#15> Successors according to CFG: BB#15 BB#17 BB#15: derived from LLVM BB %for.body156.preheader Predecessors according to CFG: BB#14 BB#17: derived from LLVM BB %for.end241 Predecessors according to CFG: BB#14 BB#16 -vreg81's VarInfo: Alive in blocks: 5, 6, 7, 8, 10, 12, 13, 19, Killed by: #0: BNE %vreg81<kill>, %ZERO, <BB#17>; CPURegs:%vreg81 2. During PHI nodes elimination, critical edge BB#14-#17 is split and BB#20 is inserted. The two terminators of BB#14 (BNE and J ) are replaced with a conditional bra...

...instructions: bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { ... // perform a final pass over the instructions and compute spill // weights, coalesce virtual registers and remove identity moves but the data structure LiveVariables::VirtRegInfo is _not_ updated. That is, VarInfo::DefInstr may point to an invalid (being coalesced) instruction. -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

On May 2, 2011, at 3:51 PM, Akira Hatanaka wrote: > - vreg81's VarInfo: > Alive in blocks: 5, 6, 7, 8, 10, 12, 13, 19, > Killed by: > #0: J <BB#17> > > > As you can see, VarInfo vreg81 is killed by the unconditional jump instruction of BB#20 when it should be killed by the newly created conditional branch in BB#14 (BEQ). Is this a bu...

...> wrote: > to those coalesced registers, it is logical that noone will ever query > the liveness of those registers (unless there is a bug somewhere in the Indeed the coalesced registers may logically not be queried since they do not appear in any operand list of the machine code, but the VarInfo::DefInst in VirtRegInfo of the _representive register_ is _not_ correct (I could trace the code at the time of writing this mail). In the other words, the patch not only have to remove the VarInfo record in VirtRegInfo, but also have to update the record for _representive register_. -- Tzu-Chien...

...als::runOnMachineFunction(MachineFunction &fn) { > ... > // perform a final pass over the instructions and compute spill > // weights, coalesce virtual registers and remove identity moves > > but the data structure LiveVariables::VirtRegInfo is _not_ updated. > That is, VarInfo::DefInstr may point to an invalid (being coalesced) > instruction. We could potentially remove those VirtRegInfos for the registers we coalesce. But since after coalescing there are no instructions refering to those coalesced registers, it is logical that noone will ever query the liveness of t...

...would like to rename a variable in a very large file (181GB) called "2013.xdf" that is saved on my external hard drive. I tried running the following code to rename variable # 2 in the file and save this change, which produced some errors that I cannot resolve: > temp.data <- rxGetVarInfo("E:/2013.xdf") > temp.data[2] <- "transsactionnumber" > rxSetVarInfo(2013fixed.data, outfile) Error: unexpected symbol in "rxSetVarInfo(2013fixed.data" > rxSetVarInfo(temp.data, outfile) Error in is.data.frame(file) : object 'outfile' not found >...

...oc parameters (local, ...) I get an error in the LiveVariable.cpp file, in the part that I think cheaks for dead code because a Variable didn't have a defined Instance to a Machine instruction. " llc: LiveVariables.cpp:86: void llvm::LiveVariables::HandleVirtRegUse(llvm::LiveVariables::VarInfo&, llvm::MachineBasicBlock*, llvm::MachineInstr*): Assertion `VRInfo.DefInst && "Register use before def!"' failed. /home/llvm/Debug/bin/llc((anonymous namespace)::PrintStackTrace()+0x1a)[0x86abeda] /home/llvm/Debug/bin/llc((anonymous namespace)::SignalHandler(int)+0xcb...

...ps? Also, is the generated code still correct if -disable-phi-elim-edge-splitting is added to the command line options? On Mon, May 2, 2011 at 5:00 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote: > > On May 2, 2011, at 3:51 PM, Akira Hatanaka wrote: > > > - vreg81's VarInfo: > > Alive in blocks: 5, 6, 7, 8, 10, 12, 13, 19, > > Killed by: > > #0: J <BB#17> > > > > > > As you can see, VarInfo vreg81 is killed by the unconditional jump > instruction of BB#20 when it should be killed by the newly created > conditiona...

...I get an error in > the LiveVariable.cpp file, in the part that I think cheaks for dead > code because a Variable didn't have a defined Instance to a Machine > instruction. > > " llc: LiveVariables.cpp:86: void > llvm::LiveVariables::HandleVirtRegUse(llvm::LiveVariables::VarInfo&, > llvm::MachineBasicBlock*, llvm::MachineInstr*): Assertion > `VRInfo.DefInst && "Register use before def!"' failed. This is a bug in your instruction selector and the assertion is telling you exactly what's wrong. Registers in MachineInstrs are also in SSA -...

...ferences memory, can I tell, given an operand, whether that operand is part of the address calculation for the instruction? Also, is there any reasonable way to get the set of machine instructions to which the output(s) of some machine instruction flows? The closest I can find is LiveVariables::VarInfo, but that only directly captures the kill points. I would have to iterate over instructions in the rest of the live range and see if the output of the defining instruction is used. Thanks! -Dave

...goo I sent an email about reordering instruction in basicblocks. And ... I was able to do it. I guess so, at least. Now when compiling my test program, llc dumps: -- llc: /home/mentat/llvm_work/llvm/lib/CodeGen/LiveVariables.cpp:155: void llvm::LiveVariables::HandleVirtRegUse(llvm::LiveVariables::VarInfo&, llvm::MachineBasicBlock*, llvm::MachineInstr*): Assertion `VRInfo.DefInst && "Register use before def!"' failed. llc((anonymous namespace)::PrintStackTrace()+0x1a)[0x86a167a] [0x6] /lib/libc.so.6(abort+0x108)[0x556d9dc8] /lib/libc.so.6(__assert_fail+0xfc)[0x556d1f6c] llc...

For adding the nop: TII->insertNoop(*BB, BB->end()); 2007/8/9, Chris Lattner <sabre at nondot.org>: > > On Thu, 9 Aug 2007, [ISO-8859-1] Emílio Wuerges wrote: > > I too believe it should not be complicated. > > But I was not being able to do it. > > Finally, after some thinking (and tinkering), this worked like a charm: > > > > MachineInstr* mi =

...d is part of the > address > calculation for the instruction? Nope, not that I know of. > Also, is there any reasonable way to get the set of machine > instructions to > which the output(s) of some machine instruction flows? The closest > I can find > is LiveVariables::VarInfo, but that only directly captures the kill > points. I > would have to iterate over instructions in the rest of the live > range and see > if the output of the defining instruction is used. On mainline, you can use the MachineRegisterInfo class (not MRegisterInfo) to walk all us...

...f the live interval analysis, I call my scheduler. After scheduling, I simply do the following: // Fix up kill information for live intervals. Rescheduling may often have // changed which instruction is a value's last use, and we must update // kill flags and the kill information in the VarInfo objects. fixKillInformation(); // Now, release the stuff we computed, and recompute it! releaseMemory(); // Then, recompute the slot indexes. There is a function renumberIndexes, // but it doesn't respect our new ordering of instructions, so do this by // completely clearing the r...

Hi, thank you for your explanations. In order to get a pre-RA scheduling, I would need something like: - LiveVars - PhiElim - TwoAddr - LiveIntervals - Coalescing - Scheduler (new) - SlotIndexing - LiveIntervals2 (new) - RegAllocMy qeustion then is, is it really so difficult to create the live intervals information, with modifications to the original algorithm, or even from scratch?

On Sep 18, 2012, at 1:45 PM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote: > I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some

Hi, I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some related commits later on, and the assertion I get on the latest trunk (r164162) differs from