Displaying 4 results from an estimated 4 matches for "varegsize".
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2013 Jun 19
2
[LLVMdev] ARM struct byval size > 64 triggers failure
...1, [r11, #12]
>>> ldr r1, [r11, #76]
>> VARegSaveSize is 16 because we store the first 16 bytes of struct byval in r0 to r3.
>>
>> For the test code/assembly I mentioned, only r1-r3 are used for struct byval. r0 used for return val.
>> So, NumGPRs = 3, VARegSize = 12, VARegSaveSize =16(4 byte offset), access of arg1 is going wrong.
>> For updated test code:
>> struct S114 check114 (int a, struct S114 arg0, struct S114* arg1) {
>> .....
>> }
>> Only r1, r2 used for struct byval, NumGPRs = 2, VARegSize = 8, VARegSaveSize =8, thi...
2013 Jun 20
1
[LLVMdev] ARM struct byval size > 64 triggers failure
...;> VARegSaveSize is 16 because we store the first 16 bytes of struct
> >>> byval in r0 to r3.
> >>> For the test code/assembly I mentioned, only r1-r3 are used for
> >>> struct byval. r0 used for return val.
> >>>
> >>> So, NumGPRs = 3, VARegSize = 12, VARegSaveSize =16(4 byte offset),
> >>> access of arg1 is going wrong.
> >>>
> >>> For updated test code:
> >>>
> >>> struct S114 check114 (*int a*, struct S114 arg0, struct S114* arg1) {
> >>>
> >>> .....
>...
2013 Jun 18
0
[LLVMdev] ARM struct byval size > 64 triggers failure
...sp, sp, #16
> Emitted by,
> if (VARegSaveSize)
> emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize, // --> VARegSaveSize is calculated in computeRegArea
> MachineInstr::FrameSetup)
>
> ARMTargetLowering::computeRegArea(..) {
> ...
> VARegSize = NumGPRs * 4;
> VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); // --> 8 byte alignment done here
> }
> Stack pointer decremented to NumGPRs*4 + alignment
> NumGPRs = 3 registers
> VARegSaveSize = 16 (after considering 8 byte alignment )
>
>...
2013 Jun 18
3
[LLVMdev] ARM struct byval size > 64 triggers failure
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