Displaying 5 results from an estimated 5 matches for "varegsavesize".
2013 Jun 19
2
[LLVMdev] ARM struct byval size > 64 triggers failure
I missed that the testing case is returning a struct.
You are right in VARegSaveSize.
For callee:
sub sp, sp, #16
push {r11, lr}
mov r11, sp
sub sp, sp, #8
str r3, [r11, #20]
str r2, [r11, #16]
str r1, [r11, #12]
ldr r1, [r11, #76]
The beginning of the input struct @ sp_at_entry - 16 - 8 + 12 = sp_at_entry -12
# of leftover bytes 67-12 = 55
r11+76 is @ sp_at_entry - 24 +...
2013 Jun 20
1
[LLVMdev] ARM struct byval size > 64 triggers failure
...rved for function return. Though, perhaps somewhere we didn't
> catch that...
>
> Would you tell me, please, your llvm revision number?
>
> -Stepan
>
> Manman Ren wrote:
> >
> > I missed that the testing case is returning a struct.
> > You are right in VARegSaveSize.
> >
> > For callee:
> > subsp, sp, #16
> > push{r11, lr}
> > movr11, sp
> > subsp, sp, #8
> > strr3, [r11, #20]
> > strr2, [r11, #16]
> > strr1, [r11, #12]
> > ldrr1, [r11, #76]
> >
> > The beginning of the input struct @ sp_a...
2013 Jun 18
0
[LLVMdev] ARM struct byval size > 64 triggers failure
...------------------------------
> sub sp, sp, #16
> push {r11, lr}
> mov r11, sp
> sub sp, sp, #8
> str r3, [r11, #20]
> str r2, [r11, #16]
> str r1, [r11, #12]
> ldr r1, [r11, #76]
VARegSaveSize is 16 because we store the first 16 bytes of struct byval in r0 to r3.
Align in computeRegArea is 8 since ABI says the stack pointer needs to be 8 byte aligned at function entry point.
But the second argument does not have to be 8 byte aligned, in fact it is 4 byte aligned for i32.
r11, #76 is equ...
2013 Jun 18
3
[LLVMdev] ARM struct byval size > 64 triggers failure
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2012 Oct 26
1
[LLVMdev] Properly handling mem-loc arguments when prologue adjusts FP.
...als.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
MachinePointerInfo::getFixedStack(FI),
false, false, false, 0));
}
...
[3] Example of prologue moving stack pointer (which the frame pointer is
then set to.)
...
if (VARegSaveSize) {
BuildMI(MBB, MBBI, dl, TII.get(ARC::SUBrsi), ARC::SP).addReg(ARC::SP)
.addImm(VARegSaveSize);
}
// Save the return address register, if necessary
if (MFI->adjustsStack()) {
BuildMI(MBB, MBBI, dl, TII.get(ARC::STrri_a)).addReg(ARC::SP)
.addImm(-UNITS_PER_WORD).ad...