Displaying 5 results from an estimated 5 matches for "vararg1".
Did you mean:
varargs
2012 Aug 06
2
[LLVMdev] ARM eabi calling convention
When I compile this program
*$ cat vararg1-main.c
typedef struct {
double d;
} S0;
S0 g1;
void foo0(int a, ...);
int main(int argc, char **argv) {
S0 s0 = { 2.0 };
foo0(1, s0);
printf("%f\n", g1.d);
* * return 0;
}*
with this command,
*$ clang -target arm-none-linux-gnueabi-gcc -ccc-clang-archs armv7
-emit-llv...
2012 Aug 07
2
[LLVMdev] ARM eabi calling convention
...cscc void (i32, ...)* @foo0(i32 1, [2 x i32] %0)
nounwindt
*
It doesn't seem that ARM backend can figure out that "[2 x i32] %0" was
originally a structure consisting of a single double field. When I run llc,
it looks like "%0" is being passed in register r1 and r2.
*$ llc vararg1-main.ll -o -
ldr r0, .LCPI0_0
ldm r0, {r1, r2}
.LCPI0_0:
.long .Lmain.s0
...
.Lmain.s0:
.long 0 @ double 2.000000e+00
*
I am running tests to see if llc targeting mips can correctly compile a
bitcode file generated by clang-arm.
One of the tests...
2012 Aug 07
0
[LLVMdev] ARM eabi calling convention
On Aug 6, 2012, at 3:21 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> When I compile this program
>
> $ cat vararg1-main.c
>
> typedef struct {
> double d;
> } S0;
>
> S0 g1;
>
> void foo0(int a, ...);
>
> int main(int argc, char **argv) {
> S0 s0 = { 2.0 };
>
> foo0(1, s0);
>
> printf("%f\n", g1.d);
>
> return 0;
> }
>
> wit...
2012 Aug 07
0
[LLVMdev] ARM eabi calling convention
...o0(i32 1, [2 x i32] %0) nounwindt
>
> It doesn't seem that ARM backend can figure out that "[2 x i32] %0" was
> originally a structure consisting of a single double field. When I run llc,
> it looks like "%0" is being passed in register r1 and r2.
>
> $ llc vararg1-main.ll -o -
>
> ldr r0, .LCPI0_0
> ldm r0, {r1, r2}
>
> .LCPI0_0:
> .long .Lmain.s0
> ...
> .Lmain.s0:
> .long 0 @ double 2.000000e+00
>
>
> I am running tests to see if llc targeting mips can correctly compile a...
2012 Aug 07
2
[LLVMdev] ARM eabi calling convention
...unwindt
>>
>> It doesn't seem that ARM backend can figure out that "[2 x i32] %0" was
>> originally a structure consisting of a single double field. When I run llc,
>> it looks like "%0" is being passed in register r1 and r2.
>>
>> $ llc vararg1-main.ll -o -
>>
>> ldr r0, .LCPI0_0
>> ldm r0, {r1, r2}
>>
>> .LCPI0_0:
>> .long .Lmain.s0
>> ...
>> .Lmain.s0:
>> .long 0 @ double 2.000000e+00
>>
>>
>> I am running tests to...