Displaying 4 results from an estimated 4 matches for "var_48".
2015 Feb 13
2
[LLVMdev] trunk's optimizer generates slower code than 3.5
...}
free(a);
return r;
}
int main(int argc, char** argv)
{
if (argc != 2) return -1;
int r = solve((int) strtol(argv[1], NULL, 10));
printf("%d solutions\n", r);
}
```
clang 3.5's result:
```
public _main
_main proc near
var_48 = qword ptr -48h
var_40 = qword ptr -40h
var_34 = dword ptr -34h
push rbp
push r15
push r14
push r13
push r12
push rbx
sub rsp, 18h...
2015 Feb 14
2
[LLVMdev] trunk's optimizer generates slower code than 3.5
...urn -1;
>> int r = solve((int) strtol(argv[1], NULL, 10));
>> printf("%d solutions\n", r);
>> }
>> ```
>>
>> clang 3.5's result:
>>
>> ```
>> public _main
>> _main proc near
>>
>> var_48 = qword ptr -48h
>> var_40 = qword ptr -40h
>> var_34 = dword ptr -34h
>>
>> push rbp
>> push r15
>> push r14
>> push r13
>> push...
2015 Feb 14
2
[LLVMdev] trunk's optimizer generates slower code than 3.5
...printf("%d solutions\n", r);
>>>> }
>>>> ```
>>>>
>>>> clang 3.5's result:
>>>>
>>>> ```
>>>> public _main
>>>> _main proc near
>>>>
>>>> var_48 = qword ptr -48h
>>>> var_40 = qword ptr -40h
>>>> var_34 = dword ptr -34h
>>>>
>>>> push rbp
>>>> push r15
>>>> push r14
>>>>...
2018 Jul 24
2
Possibility of implementing a low-level naive lock purely with LLVM atomics?
...ign 4
%0 = load atomic i32, i32* @Flag acquire, align 4
%1 = icmp eq i32 %0, 1
.......
store atomic i32 1, i32* @Flag release, align 4
```
However when inspecting the generated assembly on x86-64, the following assembly was generated:
```
mov qword [rbp+var_50], rcx
mov qword [rbp+var_48], rdx
mov rbx, rsi
mov r15, rdi
mov eax, dword [l_Flag] ; l_Flag
cmp eax, 0x1
```
Which to my best knowledge is not atomic.
I'd like to know how do I fix my frontend to make sure the locking mechanism works
Zhang
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