Displaying 4 results from an estimated 4 matches for "valuestypes".
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2005 Jul 22
2
[LLVMdev] How to partition registers into different RegisterClass?
All registers in my hardware are 4-element vector registers (128-bit).
Some are floating point registers, and the others are integer
registers.
I typedef two packed classes: [4 x float] and [4 x int], and add an
enum 'packed' to MVT::ValueType (ValuesTypes.h).
I declared all 'RegisterClass'es to be 'packed' (first argument of
RegisterClass):
def GeneralPurposeRC : RegisterClass<packed, 128, [R0, R1]>;
def INT_ReadOnlyRC : RegisterClass<packed, 128, [I0, I1]>;
def FP_ReadOnlyRC : RegisterClass<packed, 128, [F0, F...
2005 Jul 22
0
[LLVMdev] How to partition registers into different RegisterClass?
...hien Chiu wrote:
> All registers in my hardware are 4-element vector registers (128-bit).
> Some are floating point registers, and the others are integer
> registers.
>
> I typedef two packed classes: [4 x float] and [4 x int], and add an
> enum 'packed' to MVT::ValueType (ValuesTypes.h).
>
> I declared all 'RegisterClass'es to be 'packed' (first argument of
> RegisterClass):
>
> def GeneralPurposeRC : RegisterClass<packed, 128, [R0, R1]>;
> def INT_ReadOnlyRC : RegisterClass<packed, 128, [I0, I1]>;
> def FP_ReadOnlyRC : Regist...
2005 Jul 22
0
[LLVMdev] How to partition registers into different RegisterClass?
On Fri, Jul 22, 2005 at 10:29:38AM +0800, Tzu-Chien Chiu wrote:
> I' have three set of registers - read-only regs, general purpose regs
> (read and write), and write-only regs. How should I partition them
> into different RegisterClasses so that I can easy define the
> instruction?
[snip]
> def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest,
>
2005 Jul 22
2
[LLVMdev] How to partition registers into different RegisterClass?
Hi, everyone.
I' have three set of registers - read-only regs, general purpose regs
(read and write), and write-only regs. How should I partition them
into different RegisterClasses so that I can easy define the
instruction?
All RegisterClasses must be mutally exclusive. That is, a register can
only be in a RegisterClass. Otherwise TableGen will raise an error
message.
def