Displaying 11 results from an estimated 11 matches for "value_end".
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values_end
2006 Mar 19
1
[LLVMdev] Idioms for retrieving global symbols and inheritance
...symbTab.type_end(); itr1 != itrend1; itr1++ ) {
string typeName = itr1->first;
if ( lldbprfx.compare( typeName.substr( 0, 5 ) ) != 0 ) {
cerr << typeName << endl;
for ( SymbolTable::value_const_iterator itr2 =
symbTab.value_begin( itr1->second ),
itrend2 = symbTab.value_end( itr1->second ); itr2 != itrend2; itr2++ ) {
if ( lldbprfx.compare( ( itr2->first ).substr( 0, 5 ) ) != 0 ) {
cerr << "\t" << itr2->first << endl; //Produces same list that
is produced by itr1
// cerr << itr2->second->getName() <...
2007 Sep 28
0
[LLVMdev] Lowering operations to 8-bit!
On Sep 28, 2007, at 11:36 AM, <Alireza.Moshtaghi at microchip.com>
<Alireza.Moshtaghi at microchip.com> wrote:
> I moved my code to 2.1 but still the same.
> If I make ADD i16 legal, then it goes through, but it has problem
> expanding it to i8.
> Should I go ahead and customize it and do the same for all
> instructions?
> Or there is a more general thing that I
2007 Sep 28
2
[LLVMdev] Lowering operations to 8-bit!
I moved my code to 2.1 but still the same.
If I make ADD i16 legal, then it goes through, but it has problem
expanding it to i8.
Should I go ahead and customize it and do the same for all instructions?
Or there is a more general thing that I can do?
A.
-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
On Behalf Of Chris Lattner
Sent:
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...+ // which might expand to libcalls.
+ DAG.AssignTopologicalOrder();
+ for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
+ E = prior(DAG.allnodes_end()); I != next(E); ++I) {
+ bool HasVectorValue = false;
+ for (SDNode::value_iterator J = I->value_begin(); J != I->value_end(); ++J)
+ HasVectorValue |= J->isVector();
+ if (!HasVectorValue) continue;
+ SDNode* Result = I;
+ switch (I->getOpcode()) {
+ default:
+ assert(I->getOpcode() > ISD::BUILTIN_OP_END && "Unexpected node!");
+ break;
+ case ISD::UNDEF:
+...
2007 Sep 28
2
[LLVMdev] Lowering operations to 8-bit!
...erand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG){
SmallVector<SDOperand, 8> ArgValues;
SDOperand Root = Op.getOperand(0);
// Return the new list of results.
std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
Op.Val->value_end());
const Function* Fn = DAG.getMachineFunction().getFunction();
std::cout<<Op.Val->getNumValues();
std::cout<<"----------------- "<<__FUNCTION__<<" handling
FORMAL_ARGUMENTS of"<<Fn->getName()<<std::endl;std::cout.flush();
for (...
2009 May 20
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...// which might need to be unrolled.
+ DAG.AssignTopologicalOrder();
+ for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
+ E = prior(DAG.allnodes_end()); I != next(E); ++I) {
+ bool HasVectorValue = false;
+ for (SDNode::value_iterator J = I->value_begin(); J != I->value_end(); ++J)
+ HasVectorValue |= J->isVector();
+ if (!HasVectorValue) continue;
+ SDNode* Result = I;
+ switch (I->getOpcode()) {
+ default:
+ assert(I->getOpcode() > ISD::BUILTIN_OP_END && "Unexpected node!");
+ break;
+ case ISD::UNDEF:
+...
2004 May 25
1
[LLVMdev] ATTENTION: SymbolTable Change!!
...egin() and type_end() instead.
These will get you an iterator over the name/Type pairs in the
type type plane. For iteration over types, please use an iterator
named TI.
(c) To iterate over the values in one type plane (except for the
plane of types), use value_begin(Type*) and value_end(Type*).
These methods will get you an iterator over the name/Value
pairs in the single type plane given by the arguments. For
iterating over values, please use an iterator named VI.
4. Some functionality (like "strip") has been moved into the
SymbolTable. This mean...
2016 Aug 19
2
Crash on opening mailbox
...arsed_header (field_idx=<optimized out>, mail=<optimized out>) at index-mail-headers.c:585
value = 0x7f328d331616 <pool_system_malloc+22> "H\205\300t\025[\303\017\037"
lines_count = <optimized out>
value_start = <optimized out>
value_end = <optimized out>
i = <optimized out>
first_line_idx = <optimized out>
#7 index_mail_get_raw_headers (mail=mail at entry=0x7d7e80, field=field at entry=0x7f328d663446 "Message-Id", value_r=value_r at entry=0x7ffc6c9df540) at index-mail-headers.c:656...
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...// which might need to be unrolled.
+ DAG.AssignTopologicalOrder();
+ for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
+ E = prior(DAG.allnodes_end()); I != next(E); ++I) {
+ bool HasVectorValue = false;
+ for (SDNode::value_iterator J = I->value_begin(); J != I->value_end(); ++J)
+ HasVectorValue |= J->isVector();
+ if (!HasVectorValue) continue;
+ SDNode* Result = I;
+ switch (I->getOpcode()) {
+ default:
+ assert(I->getOpcode() > ISD::BUILTIN_OP_END && "Unexpected node!");
+ break;
+ case ISD::UNDEF:
+...