search for: valanalysis

Displaying 6 results from an estimated 6 matches for "valanalysis".

[LLVMdev] Assert in live update from MI scheduler.
2012 Jun 12
2
[LLVMdev] Assert in live update from MI scheduler.
...I am working on a release based on the branch 3.1 version of code. Unfortunately it has enough differences that exact rev does not apply. I am hitting an assert in liveness update with seemingly trivial code (attached). /local/mnt/workspace/slarin/tools/llvm-mainline-merged/lib/CodeGen/LiveInter valAnalysis.cpp:1078: void llvm::LiveIntervals::HMEditor::moveAllRangesFrom(llvm::MachineInstr*, llvm::SlotIndex): Assertion `validator.rangesOk() && "moveAllOperandsFrom broke liveness."' failed. The code being scheduled (function "push") is trivial: # Machine code for functi...
[LLVMdev] Assert in live update from MI scheduler.
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...sed on the branch 3.1 version of code. > Unfortunately it has enough differences that exact rev does not apply. > I am hitting an assert in liveness update with seemingly trivial code > (attached). > > /local/mnt/workspace/slarin/tools/llvm-mainline-merged/lib/CodeGen/LiveInter > valAnalysis.cpp:1078: void > llvm::LiveIntervals::HMEditor::moveAllRangesFrom(llvm::MachineInstr*, > llvm::SlotIndex): Assertion `validator.rangesOk() && "moveAllOperandsFrom > broke liveness."' failed. > > The code being scheduled (function "push") is trivial: &...
[LLVMdev] scoreboard hazard det. and instruction groupings
2012 Jun 11
0
[LLVMdev] scoreboard hazard det. and instruction groupings
On Jun 11, 2012, at 12:07 PM, Hal Finkel <hfinkel at anl.gov> wrote: > Looking at VLIWPacketizerList::PacketizeMIs, it seems like the > instructions are first scheduled (via some external scheme?), and then > packetized 'in order'. Is that correct? Anshu? > In the PowerPC grouping scheme, resources are assigned on a group > basis (by the instruction dispatching
[LLVMdev] Assert in live update from MI scheduler.
2012 Jun 13
4
[LLVMdev] Assert in live update from MI scheduler.
...fortunately it has enough differences that exact rev does not > apply. > > I am hitting an assert in liveness update with seemingly trivial code > > (attached). > > > > /local/mnt/workspace/slarin/tools/llvm-mainline- > merged/lib/CodeGen/Liv > > eInter > > valAnalysis.cpp:1078: void > > llvm::LiveIntervals::HMEditor::moveAllRangesFrom(llvm::MachineInstr*, > > llvm::SlotIndex): Assertion `validator.rangesOk() && > > "moveAllOperandsFrom broke liveness."' failed. > > > > The code being scheduled (function "p...
[LLVMdev] scoreboard hazard det. and instruction groupings
2012 Jun 11
3
[LLVMdev] scoreboard hazard det. and instruction groupings
On Mon, 11 Jun 2012 10:48:18 -0700 Andrew Trick <atrick at apple.com> wrote: > On Jun 11, 2012, at 9:30 AM, Hal Finkel <hfinkel at anl.gov> wrote: > > > I'm considering writing more-detailed itineraries for some PowerPC > > CPUs that use the 'traditional' instruction grouping scheme. In > > essence, this means that multiple instructions will stall
[LLVMdev] Assert in live update from MI scheduler.
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...at exact rev does not > > apply. > > > I am hitting an assert in liveness update with seemingly trivial > > > code (attached). > > > > > > /local/mnt/workspace/slarin/tools/llvm-mainline- > > merged/lib/CodeGen/Liv > > > eInter > > > valAnalysis.cpp:1078: void > > > > llvm::LiveIntervals::HMEditor::moveAllRangesFrom(llvm::MachineInstr* > > > , > > > llvm::SlotIndex): Assertion `validator.rangesOk() && > > > "moveAllOperandsFrom broke liveness."' failed. > > > > > &...