search for: v8

.... The most usable I've seen is this: Core was generated by `/usr/lib64/chromium-browser/chromium-browser --type=renderer --crashpad-handler'. Program terminated with signal SIGSEGV, Segmentation fault. warning: Section `.reg-xstate/3' in core file too small. #0 0x0000555abfb91cdd in v8::internal::ThreadIsolation::RegisterJitPage(unsigned long, unsigned long) () [Current thread is 1 (Thread 0x7f707f3fe640 (LWP 3))] (gdb) bt #0 0x0000555abfb91cdd in v8::internal::ThreadIsolation::RegisterJitPage(unsigned long, unsigned long) () #1 0x0000555abfcec796 in v8::internal::MemoryAllocat...

...a.lang.ref.Reference$ReferenceHandler.run(Reference.java:110) "Signal dispatcher" (TID:0x28d6a330, sys_thread_t:0x8097280, state:CW) prio=5 "main" (TID:0x28d6a1b0, sys_thread_t:0x8055080, state:R) prio=5 at java.lang.Long.parseLong(Long.java:299) at com.sun.tools.javac.v8.util.Convert.string2long(Convert.java:41) at com.sun.tools.javac.v8.parser.Parser.literal(Parser.java:280) at com.sun.tools.javac.v8.parser.Parser.term3(Parser.java:630) at com.sun.tools.javac.v8.parser.Parser.term2(Parser.java:472) at com.sun.tools.javac.v8.parser.Parser.term1(Parser.java:441)...

...ast, the?following part?looks ugly. ccl[,m]<-lia[,1]*lia[,2]*lia[,3]*lia[,4]*lia[,5] any suggestion are appreciated. The Loop code: for(m in 1:ns){ ?for(i in 1:nt){ ??? vbar2[,i]=a[1]+???? eta[m]+acedu[,i]*a[2]+acwrk[,i]*a[3] ??? vbar3[,i]=b[1]+b[2]*eta[m]+acedu[,i]*b[3]+acwrk[,i]*b[4] ??? v8[,i]=1+exp(vbar2[,i])+exp(vbar3[,i]) ????? for(j in 1:n){ ?? ???? ? if (edu[j,i]==1) lia[j,i]=1/v8[j,i] ????????? if (wrk[j,i]==1) lia[j,i]=exp(vbar2[j,i])/v8[j,i] ????????? if (home[j,i]==1) lia[j,i]=exp(vbar3[j,i])/v8[j,i] ???? } ?? ccl[,m]<-lia[,i]*ccl[,m] ?} } The Matrix code: for(m in 1:ns...

Sadly the latest optimization broke completely everything. The asm code isn't gas compliant. the libFLAC linker script has a typo, disabling the asm optimization and/or altivec won't let a correct build anyway. Instant fixes for the asm stuff: sed -i -e"s:;:\#:" on the lpc_asm.s to load address instead of addis+ori you could use lis and la and PLEASE use the @l(register)

Hi, I have problems compiling speex 1.2rc1: > /opt/studio/SOS11/SUNWspro/bin/cc -DHAVE_CONFIG_H -I. -I. - > I.. -I../include -I../include -I.. -I/opt/csw/include -I/opt/csw/ > include -xO3 -xarch=v8 -I/opt/csw/include -c skeleton.c > /bin/bash ../libtool --mode=link /opt/studio/SOS11/SUNWspro/bin/cc - > xO3 -xarch=v8 -I/opt/csw/include -xarch=v8 -L/opt/csw/lib -o > speexenc speexenc.o wav_io.o skeleton.o ../libspeex/libspeex.la ../ > libspeex/libspeexdsp.la -L/opt/csw/lib -l...

...r word size slwi r4,r4,2 add r4,r4,r8 ; r4 = data+data_len mfspr r0,256 ; cache old vrsave addis r31,0,hi16(0xfffffc00) ori r31,r31,lo16(0xfffffc00) mtspr 256,r31 ; declare VRs in vrsave cmplw cr0,r8,r4 ; i<data_len bc 4,0,L1400 ; load coefficients into v0-v7 and initial history into v8-v15 li r31,0xf and r31,r8,r31 ; r31: data%4 li r11,16 subf r31,r31,r11 ; r31: 4-(data%4) slwi r31,r31,3 ; convert to bits for vsro li r10,-4 stw r31,-4(r9) lvewx v0,r10,r9 vspltisb v18,-1 vsro v18,v18,v0 ; v18: mask vector li r31,0x8 lvsl v0,0,r31 vsldoi v0,v0,v0,12 li r31,0xc lvsl...

Hi, I am still on LLVM v6 as v7 ORC api changes were not backward compatible. Has the ORC api stabilized now with v8, or is it still under flux? Thanks and Regards Dibyendu

Dear R-list, I have a dataset, say (the real dataset is 20 columns,110200 rows). > my.reducedID V1 V2 V3 V4 V5 V6 V7 V8 V9 [1,] 1 0 0 1 14 3 1 0 2 [2,] 2 0 0 1 14 3 1 0 2 [3,] 0 1 0 1 14 2 1 0 2 [4,] 0 0 1 1 14 3 1 0 2 [5,] 0 1 1 0 14 2 1 0 2 [6,] 0 0 0 1 14 3 1 0 2 [7,] 0 0 0 1 0 3 1 0 2 [8,] 0 0 0 1 1 3 1 0 2 [9,]...

Hello, I'm looking for a solution for the following problem: 1) I have a folder with several csv files; each contains a set of measurement values 2) The measurements of each file belong to a position in a two dimensional matrix (lets say "B02.csv" belongs to position 2,2 3) The size of the matrix is fix 4) I cannot assure to have a csv file for each position 5) Each position

...CodeEmitter.cpp and that's the problem I'm facing. The triple I'm using is "armv7-unknown-linux-gnueabi" and the bitcode I'm dealing with is: ; ModuleID = 'CRYO jit' target triple = "armv7a-unknown-linux-gnueabi" define i32 @execute(i8* %JNIEnv, i8* %v8) { entry: %litTemp = alloca i32 %v0_INTEGER = alloca i32 %v4_INTEGER = alloca i32 %v5_INTEGER = alloca i32 %v2_INTEGER = alloca i32 %v6_INTEGER = alloca i32 %v5_POINTER = alloca i8* %v1_INTEGER = alloca i32 %v3_INTEGER = alloca i32 %v7_INTEGER = alloca i32 store i3...

...ation, and when he tries to save it, he gets a "share violation" error. (other people have this problem too). This error happens since I upgraded the SAMBA server from 3.0.14a to 3.0.21c. smbstatus for this file: 32613 DENY_WRITE 0x20089 RDONLY NONE /home/user/J84400os-V8 Thu Jun 15 10:46:05 2006 Samba log when trying to save the file: [2006/06/15 10:50:44, 2] smbd/open.c:open_file(350) user1 opened file J84400os-V8 read=Yes write=No (numopen=12) [2006/06/15 10:50:44, 3] smbd/oplock_linux.c:linux_set_kernel_oplock(161) linux_set_kernel_oplock: Refused oplock on...

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...W, what test do you use to produce the hang condition? > > Running ebizzy on 2 of the vms simultaneously (for sometime in > repeated loop) could reproduce it. > Yes, I am able to reproduce the hang problem with ebizzy. BTW, could you try to apply the attached patch file on top of the v8 patch series to see if it can fix the hang problem? > >> What is the baseline for the performance improvement? Is it without the >> unfair lock and PV qspinlock? > > Baseline was 3.14-rc8 without any of the qspin patch series. > Does the baseline have PV ticketlock or wit...

...W, what test do you use to produce the hang condition? > > Running ebizzy on 2 of the vms simultaneously (for sometime in > repeated loop) could reproduce it. > Yes, I am able to reproduce the hang problem with ebizzy. BTW, could you try to apply the attached patch file on top of the v8 patch series to see if it can fix the hang problem? > >> What is the baseline for the performance improvement? Is it without the >> unfair lock and PV qspinlock? > > Baseline was 3.14-rc8 without any of the qspin patch series. > Does the baseline have PV ticketlock or wit...

...I have not used R, and I need a result in the next one or two hour... I have a table which I have loaded with read.table, and I want to make the mean of its columns. > slides <- read.table("slides.txt") > slides [1:5,] V1 V2 V3 V4 V5 V6 V7 V8 1 PLB00090AA02 0.147 0.018 0.046 0.064 -0.018 -0.008 -0.063 2 PLB00090BC08 0.171 0.011 -0.001 0.009 0.052 0.032 -0.065 3 PLB00090CG02 0.029 -0.014 -0.042 0.006 0.024 -0.009 -0.043 4 PLB00091AA08 0.033 0.050 -0.022 -0.002 0.038 0.015 -0.037 5 PLB00091BE02 0.183 0.039 0.052 -0.014 -0.03...

...r-covar matrices are statistically the same? Below are a pair of two matrices, from several others. Thank you in advance for any input. Aldi First group var-covar matrix (the data were under treatment a) v1 v2 v3 v4 v5 v6 v7 v8 v9 v1 730.87 3.406 -283.41 -74.68 107.57 -1355.13 -112.46 14.000 5.776 v2 3.41 24.950 105.45 -121.31 -307.68 -285.40 29.65 -2.500 -7.796 v3 -283.41 105.451...

...is too easy or irrelevant. I am doing a simulation study and I need to read a data file that can be easily read by SAS. So, what I try to do is to execute SAS in R and then read the output of SAS to R. I try the following code but it didn't work. system("c:\\program files\\sas institute\\v8\\sas.exe test") can anyone give me some help with this? Thanks. Davoid **************************************************************************** This email may contain confidential material. If you were not an intended recipient, Please notify the sender and delete all copies. We ma...

Dear all, I have a dataset. I want to make barplot from this data. Zero1 <- " V1 V2 V3 V4 V5 V6 V7 V8 V9 1 1 0 0 0 1 0 0 0 Positive 2 0 0 1 0 1 0 1 1 Negative 3 0 0 1 0 0 0 1 1 Positive 4 0 1 0 1 1 1 0 1 Negative 5 0 0 1 0 1 1 0 0 Positive 6 0 1 0 0 1 1 1 1 Negative 7 1 0 1 1 1 1 1 1 Negative 8 0 0 0 0 1 0 0 1 Negative 9...

...ed, Apr 02, 2014 at 09:27:29AM -0400, Waiman Long wrote: >> N.B. Sorry for the duplicate. This patch series were resent as the >> original one was rejected by the vger.kernel.org list server >> due to long header. There is no change in content. >> >> v7->v8: >> - Remove one unneeded atomic operation from the slowpath, thus >> improving performance. >> - Simplify some of the codes and add more comments. >> - Test for X86_FEATURE_HYPERVISOR CPU feature bit to enable/disable >> unfair lock. >> - R...

...ed, Apr 02, 2014 at 09:27:29AM -0400, Waiman Long wrote: >> N.B. Sorry for the duplicate. This patch series were resent as the >> original one was rejected by the vger.kernel.org list server >> due to long header. There is no change in content. >> >> v7->v8: >> - Remove one unneeded atomic operation from the slowpath, thus >> improving performance. >> - Simplify some of the codes and add more comments. >> - Test for X86_FEATURE_HYPERVISOR CPU feature bit to enable/disable >> unfair lock. >> - R...