search for: v64i32

Hello, i am experimenting with the increase in register/ vector width to 64 elements of 32 bits instead of 16 in x86 backend. for eg. i have a loop with 65 iterations; if my IR generates v64i32 and 1 scalar, still the backend breaks the v64i32 into 4 v16i32. i want it to retain v64i32. like if there are 128 elements in loop then it should break it into 2 v64i32 instructions. in order to do this i have made necessary changes in X86ISelLowering.cpp. and rebuild llvm. then when i use the co...

...gt; <mailto:hahmed2305 at gmail.com>> wrote: > > Hello, > i am experimenting with the increase in register/ vector width to > 64 elements of 32 bits instead of 16 in x86 backend. > for eg. > i have a loop with 65 iterations; > if my IR generates v64i32 and 1 scalar, still the backend breaks > the v64i32 into 4 v16i32. i want it to retain v64i32. like if > there are 128 elements in loop then it should break it into 2 > v64i32 instructions. > > in order to do this i have made necessary changes in > X86ISelLower...

...hmed" <hahmed2305 at gmail.com> wrote: >> >> Hello, >> i am experimenting with the increase in register/ vector width to 64 >> elements of 32 bits instead of 16 in x86 backend. >> for eg. >> i have a loop with 65 iterations; >> if my IR generates v64i32 and 1 scalar, still the backend breaks the >> v64i32 into 4 v16i32. i want it to retain v64i32. like if there are 128 >> elements in loop then it should break it into 2 v64i32 instructions. >> >> in order to do this i have made necessary changes in X86ISelLowering.cpp. >&...

...t;>> >>>> Hello, >>>> i am experimenting with the increase in register/ vector width to 64 >>>> elements of 32 bits instead of 16 in x86 backend. >>>> for eg. >>>> i have a loop with 65 iterations; >>>> if my IR generates v64i32 and 1 scalar, still the backend breaks the >>>> v64i32 into 4 v16i32. i want it to retain v64i32. like if there are 128 >>>> elements in loop then it should break it into 2 v64i32 instructions. >>>> >>>> in order to do this i have made necessary chang...

...f64: return lowerV32F64VectorShuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); case MVT::v64f32: return lowerV64F32VectorShuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); case MVT::v32i64: return lowerV32I64VectorShuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); case MVT::v64i32: return lowerV64I32VectorShuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); default: llvm_unreachable("Not a valid P x86 vector type!"); } } static SDValue lowerV64I32VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, const...

...d as follows: def GATHER_256B : I<0x68, MRMSrcMem, (outs VR_2048:$dst, VK64WM:$mask_wb), (ins VR_2048:$src1, VK64WM:$mask, i2048mem:$src2), "GATHER_256B\t{$src2, {$dst} {${mask}}|${dst} {${mask}}, $src2}", [(set VR_2048:$dst, VK64WM:$mask_wb, (v64i32 (masked_gather (VR_2048:$src1), VK64WM:$mask, addr:$src2)))], IIC_MOV_MEM>, TA; def: Pat<(v64f32 (masked_gather (VR_2048:$src1), (VK64WM:$mask),(addr:$src2))), (GATHER_256B VR_2048:$src1, VK64WM:$mask, addr:$src2)>; Now getting this error: llvm...

...orrect now?? def GATHER_256B : I<0x68, MRMSrcMem, (outs VR_2048:$dst, _.KRCWM:$mask_wb), (VR_2048:$src1, _.KRCWM:$mask, ins i2048mem:$src2), "GATHER_256B\t{$src2, {$dst}{${mask}}|${dst} {${mask}}, $src2}"), [(set VR_2048:$dst, _.KRCWM:$mask_wb, (v64i32 (GatherNode (VR_2048:$src1), _.KRCWM:$mask, VR_2048:$src2))], IIC_MOV_MEM>, TA; def: Pat<(v64f32 (GatherNode addr:$src2)), (GATHER_256B addr:$src2)>; Thank You On Mon, Aug 7, 2017 at 2:57 AM, Craig Topper <craig.topper at gmail.com> wrote:...

i want to implement gather for v64i32. i wrote following code. def GATHER_256B : I<0x68, MRMSrcMem, (outs VR_2048:$dst), (ins i2048mem:$src), "GATHER_256B\t{$src, $dst|$dst, $src}", [(set VR_2048:$dst, (v64i32 (masked_gather addr:$src)))], IIC_MOV_MEM>, TA; de...

Thank you so much. it run fine. Can you please resolve following issue; I now have support for v2048i32 but my backend supports v64i32 so ultimately v2048i32 needs to be split into 32 v64i32 instructions. the only difference between 2 is if its orginally v2048i32 i want my registers assignment from REG_A set. if its v64i32 originally, then i want registers from set REG_B. How to accomplish this??? I am really stuck at this poin...

...512 vector instructions are written in x86instravx512. i need to define my vector instructions so i wrote; def VMOV_256B_RM : I<0x6F, MRMSrcMem, (outs VR2048:$dst), (ins i32mem:$src), "vmov_256B_rm\t{$src, $dst|$dst, $src}", [(set VR2048:$dst, (v64i32 (scalar_to_vector (loadi32 addr:$src))))], IIC_MOV_MEM>, EVEX; def VMOV_256B_MR : I<0x7F, MRMDestMem, (outs), (ins i32mem:$dst, VR2048:$src), "vmov_256B_mr\t{$src, $dst|$dst, $src}", [(store (i32 (bitconvert VR2048:$src)),...

...ternatives but could not succeed. Also I have asked this question many times but no one responds. Is there something wrong with this?? Kindly guide me. Thank You On Wed, Jul 12, 2017 at 12:56 AM, hameeza ahmed <hahmed2305 at gmail.com> wrote: > here by the ********my backend supports v64i32 i mean my hardware. > > On Wed, Jul 12, 2017 at 12:49 AM, hameeza ahmed <hahmed2305 at gmail.com> > wrote: > >> Thank you so much. it run fine. >> Can you please resolve following issue; >> >> I now have support for v2048i32 >> but my backend support...

...rc, $dst|$dst, $src}", [], >> IIC_XADD_REG>, TB; >> >> what is llc_xadd_reg here? >> >> >> >> On Sat, Jul 8, 2017 at 8:48 AM, Craig Topper <craig.topper at gmail.com> >> wrote: >> >>> Change the i32 in the store pattern to v64i32. >>> >>> On Fri, Jul 7, 2017 at 8:41 PM hameeza ahmed <hahmed2305 at gmail.com> >>> wrote: >>> >>>> Thank you. i understood how avx512 vector instructions are written in >>>> x86instravx512. i need to define my vector instructions so...

...backend. Here i need to define vector load and stores for 64 i32 elements. so in x86instrinfo.td i wrote; def VMOV_256B_RM : I<0x6F, MRMSrcMem, (outs VR2048:$dst), (ins i32mem:$src), "vmov_256B_rm\t{$src, $dst|$dst, $src}", [(set VR2048:$dst, (v64i32 (scalar_to_vector (loadi32 addr:$src))))], IIC_MOV_MEM>, EVEX; def VMOV_256B_MR : I<0x7F, MRMDestMem, (outs), (ins i32mem:$dst, VR2048:$src), "vmov_256B_mr\t{$src, $dst|$dst, $src}", [(store (i32 (bitconvert VR2048:$src)),...

You are right. But when i defined my instruction as follows: def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, VEX_4V; I get opcode conflicts? Then what to do? On Tue, Sep 5, 2017 at 3:51 AM, Craig Topper <craig.topper at gmail.com> wrote: > That is not correct. You should add VEX_4V. TA tells the X86 encoder that > the instruction opcode belon...

...t;>>>>> On Sat, Jul 8, 2017 at 8:48 AM, Craig Topper < >>>>>>>>>>>> craig.topper at gmail.com> wrote: >>>>>>>>>>>> >>>>>>>>>>>>> Change the i32 in the store pattern to v64i32. >>>>>>>>>>>>> >>>>>>>>>>>>> On Fri, Jul 7, 2017 at 8:41 PM hameeza ahmed < >>>>>>>>>>>>> hahmed2305 at gmail.com> wrote: >>>>>>>>>>>>> &...

...: > >> You are right. But when i defined my instruction as follows: >> def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins >> VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, >> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 >> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, VEX_4V; >> >> I get opcode conflicts? Then what to do? >> >> On Tue, Sep 5, 2017 at 3:51 AM, Craig Topper <craig.topper at gmail.com> >> wrote: >> >>> That is not correct. You should add VEX...

...right. But when i defined my instruction as follows: >>>> def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins >>>> VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, >>>> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 >>>> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, VEX_4V; >>>> >>>> I get opcode conflicts? Then what to do? >>>> >>>> On Tue, Sep 5, 2017 at 3:51 AM, Craig Topper <craig.topper at gmail.com> >>>> wrote: >>>&...

...d my instruction as follows: >>>>>> def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins >>>>>> VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, >>>>>> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 >>>>>> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, VEX_4V; >>>>>> >>>>>> I get opcode conflicts? Then what to do? >>>>>> >>>>>> On Tue, Sep 5, 2017 at 3:51 AM, Craig Topper <craig.topper at gmail.com&g...

Thank You. My add instruction has TA as follows: def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, TA; so i defined; bool HasTA = TSFlags & X86II::TA; in x86MCCodeEmitter.cpp then used this condition; if(HasTA) ++SrcRegNum; now getting no error. please tell me whether my method is correct? Also please confirm this whether i need...

...ows: >>>>>>>> def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins >>>>>>>> VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, >>>>>>>> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 >>>>>>>> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, VEX_4V; >>>>>>>> >>>>>>>> I get opcode conflicts? Then what to do? >>>>>>>> >>>>>>>> On Tue, Sep 5, 2017 at 3:51 AM, Crai...